View ADE7169ASTZF16-RL_3778242.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

single-phase energy measurement ic with 8052 mcu, rtc and lcd driver preliminary technical data ade7169f16 rev. prd 09/06 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2006 analog devices, inc. all rights reserved. general features wide supply voltage operation 2.4 to 3.7v battery supply input with automatic switch-over reference 1.2 v 1% (drift 50 ppm/c maximum) 64-lead quad flat (lqfp) or chip scale (lcsp) lead free packages operating temperature -40c to 85c energy measurement features high accuracy active, reactive energy measurement ic, supports iec 62053-21, 62053-22, 62053-23 two differential inputs with pgas to support shunt, current transformer and di/dt current sensors selectable digital integrator to support di/dt current sensor digital parameters for gain, offset and phase compensation selectable no-load threshold level for watt, va, and var anti-creep less than 0.1% error on active energy over a dynamic range of 1000 to 1 @ 25c less than 0.5% error on reactive energy over a dynamic range of 1000 to 1 @ 25c less than 0.5% error on rms measurements over a dynamic range of 1000 to 1 for current and 100:1 for voltage @ 25c auto-calibration of offsets high frequency outputs supply proportional to irms, active, reactive or apparent power proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time temperature monitoring microprocessor features 8052 based core single-cycle 4mips 8052 core 8052 compatible instruction set 32.768 khz external crystal with on-chip pll two external interrupt sources external reset pin real time clock counter for seconds, minutes and hours automatic battery switchover for rtc back up ultra-low battery supply current < 1 a software clock calibration with temperature and offset compensation integrated lcd driver 104-segment with 2, 3 or 4 multiplexer 3v/5v driving capability internally generated lcd drive voltages temperature and supply compensated drive voltages low power battery mode wake-up from i/o and uart lcd driver capability on-chip peripherals uart, spi or i 2 c watch-dog timer power supply monitoring with user selectable levels memory: 16kbytes flash memory, 512 bytes ram development tools single pin emulation ide based assembly and c source debugging general description the ade7169f16 integrates analog devices energy (ade) metering ic analog front end and fixed function dsp solution with an enhanced 8052 mcu core, a rtc, an lc d driver and all the peripherals to make an electronic energy meter with lcd display with a single part. the ade energy measurement core includes active, reactive, appare nt energy calculations, as well as voltage and current rms measurements. this information is ready to use for energy billing by using built-in energy scalars. many power line supervisory features like sag, peak, zero-crossing are also incl uded in the energy measurement dsp to simplify energy meter design. the microprocessor functionality includes a single cycle 8052 co re, a real time clock with a power supply back-up pin, a uart, and a spi or i 2 c interface. the ready to use information from the ade core reduces the program memory size requirement thus making it easy to integrate complicated design in 16k bytes of flash memory. the ade7169f16 also includes a 104-segment lcd driver. this driv er generates voltages capable of driving 5v lcds.
ade7169f16 preliminary technical data rev. prd | page 2 of 140 functional block diagram 1 - p i n e m u l a t o r 1.20v ref adc adc ipa in vp vn r e f i n / o u t energy measurement dsp pga1 pga2 osc pll com0 ... com3 . . . . c f 1 c f 2 temp adc battery adc ldo por 3v/5v lcd charge pump v sw adc adc pga1 ipb v d c i n temp sensor v bat power supply control & monitoring v d d v s w o u t ldo v i n t d v i n t a r e s e t dgnd agnd t x d uart serial port uart timer e a downloader debugger lcdva lcdvb lcdvc . . . fp0 ... fp15 rtc 1 4 15 17 18 3 8 4 1 4 0 3 9 4 2 4 3 5 7 s s s c l k m i s o m o s i / s d a t a 55 53 52 49 50 54 63 58 3 6 4 4 6 2 5 1 5 6 5 9 6 1 6 0 6 4 3 7 r x d s d e n 13 14 20 35 11 12 9 10 7 8 5 6 7 t 2 8 t 2 e x 3 9 t 0 3 8 t 1 lcdvp1 lcdvp2 16 19 x t a l 1 4 7 4 6 x t a l 2 i n t 0 4 8 4 5 i n t 1 fp16 fp17 fp23 fp22 fp21 fp20 fp19 fp18 fp25 fp24 4 5 4 2 4 3 1 1 p 0 . 7 ( s s / t 1 ) p 0 . 6 ( s c l k / t 0 ) p 0 . 5 ( m i s o ) p 0 . 4 ( m o s i / s d a t a ) 3 9 3 8 4 1 p 0 . 0 ( b c t r l / i n t 1 ) 4 0 3 7 6 5 3 6 p 1 . 0 ( r x d ) p 1 . 1 ( t x d ) p 1 . 2 ( f p 2 5 ) p 1 . 3 ( t 2 e x / f p 2 4 ) 9 p 1 . 6 ( f p 2 1 ) 1 0 p 1 . 7 ( f p 2 0 ) 7 p 1 . 4 ( t 2 / f p 2 3 ) 8 p 1 . 5 ( f p 2 2 ) 14 p2.0 (fp18) p2.1 (fp17) p2.2 (fp16) p2.3 (sden) 13 12 p 0 . 1 ( f p 1 9 ) p 0 . 2 ( c f 1 ) p 0 . 3 ( c f 2 ) 44 figure 1. ade7169f16 functional block diagram
preliminary technical data ade7169f16 rev. prd | page 3 of 140 table of content functional block diagram .............................................2 table of content .................................................................................3 ade7169f16specifications .........................................................7 timing specifications .....................................................................11 absolute maximum ratings ..........................................................18 esd caution ................................................................................18 terminology.....................................................................................19 measurement error.....................................................................19 phase error between channels .................................................19 power supply rejection..............................................................19 adc offset error........................................................................19 gain error ....................................................................................19 pin descriptions ..............................................................................20 sfr mapping....................................................................................22 power management ........................................................................23 power management register details ..........................................23 power supply architecture ........................................................25 battery switchover ......................................................................26 switching from v dd to v bat ...................................................26 switching from v bat to v dd ...................................................26 power supply monitor interrupt (psm) ..................................26 battery switchover and power supply restored psm interrupt ...................................................................................27 v sw monitor psm interrupt ..................................................27 v bat monitor psm interrupt .................................................27 v dcin monitor psm interrupt................................................27 sag monitor psm interrupt.................................................28 using the power supply features ...............................................28 operating modes.............................................................................31 psm0 (normal mode) ................................................................31 psm1 (battery mode) .................................................................31 psm2 (sleep mode) ....................................................................31 3.3v peripherals and wakeup events.......................................32 transitioning between operating modes................................32 automatic battery switchover (psm0 to psm1)................32 entering sleep mode (psm1 to psm2)................................33 servicing wakeup events (psm2 to psm1) ........................33 automatic switch to v dd (psm2 to psm0).........................33 automatic switch to v dd (psm1 to psm0).........................33 using the power management features ....................................33 energy measurement......................................................................34 access to energy measurement sfr............................................34 access to internal energy measurement registers...................34 writing to internal energy measurement registers ............34 reading internal energy measurement registers ...............34 energy measurement registers...........................................35 energy measurement internal registers details.......................37 analog inputs ..............................................................................41 analog to digital conversion ...................................................42 anti-aliasing filter..................................................................43 adc transfer function .........................................................43 current channel adc...........................................................43 voltage channel adc............................................................44 channel sampling...................................................................44 fault detection ............................................................................44 channel selection indication ................................................44 fault indication .......................................................................45 fault with active input greater than inactive input..........45 fault with inactive input greater than active input..........45 calibration concerns .............................................................45 di/dt current sensor and digital integrator............................45 power quality measurements.....................................................47 zero-crossing detection .......................................................47
ade7169f16 preliminary technical data rev. prd | page 4 of 140 zero-crossing timeout......................................................... 47 period measurement.............................................................. 47 line voltage sag detection ................................................... 48 peak detection........................................................................ 48 peak level record .................................................................. 49 phase compensation.................................................................. 49 ade7169f16 rms calculation................................................ 49 current channel rms calculation...................................... 50 current channel rms offset compensation ..................... 50 voltage channel rms calculation ....................................... 51 voltage channel rms offset compensation ...................... 51 active power calculation .......................................................... 51 active power gain calibration............................................... 52 active power offset calibration............................................. 52 active power sign detection.................................................. 52 active power no-load detection.......................................... 52 active energy calculation .................................................... 53 integration time under steady load .................................... 54 active energy accumulation modes..................................... 54 active energy pulse output ................................................... 55 line cycle active energy accumulation mode..................... 55 reactive power calculation ...................................................... 56 reactive power gain calibration ........................................... 57 reactive power offset calibration ......................................... 57 sign of reactive power calculation ..................................... 57 reactive power sign detection .............................................. 57 reactive power no-load detection ...................................... 58 reactive energy calculation................................................. 58 integration time under steady load .................................... 59 reactive energy accumulation modes ................................. 59 reactive energy pulse output................................................ 60 line cycle reactive energy accumulation mode ................. 60 apparent power calculation..................................................... 60 apparent power offset calibration ..................................... 61 apparent energy calculation ............................................... 61 integration times under steady load................................. 62 apparent energy pulse output .............................................. 62 line apparent energy accumulation.................................. 62 apparent power no-load detection .................................... 63 energy-to-frequency conversion............................................ 63 pulse output configuration ................................................... 63 pulse output characteristic.................................................... 64 energy register scaling............................................................... 64 energy measurement interrupts............................................... 64 temperature, battery and supply voltage measurements ........ 66 temperature measurement ....................................................... 68 single temperature measurement ....................................... 68 background temperature measurements........................... 68 temperature adc in psm1 and psm2 .............................. 68 temperature adc interrupt................................................. 69 battery measurement ................................................................. 69 single battery measurement................................................. 69 background battery measurements..................................... 69 battery adc in psm1 and psm2 ........................................ 69 battery adc interrupt .......................................................... 69 supply voltage measurement ................................................... 69 single supply voltage measurement .................................... 70 background supply voltage measurements ....................... 70 supply voltage adc in psm1 and psm2 ........................... 70 supply voltage adc interrupt.............................................. 70 8052 mcu core architecture.................................................... 71 mcu registers............................................................................. 71 basic 8052 registers ................................................................... 72 standard 8052 sfrs.................................................................... 73 memory overview ..................................................................... 74 addressing modes...................................................................... 75
preliminary technical data ade7169f16 rev. prd | page 5 of 140 instruction set..............................................................................76 read-modify-write instructions ..............................................79 instructions that affect flags ....................................................79 interrupt system ..............................................................................82 standard 8051 interrupt architecture......................................82 ade7169f16 interrupt architecture .......................................82 interrupt sfr register list...........................................................82 interrupt priority.........................................................................84 interrupt flags .............................................................................84 interrupt vectors .........................................................................87 watch dog functionality.........................................................87 watchdog timer interrupt ....................................................87 context saving.............................................................................87 lcd driver ......................................................................................88 lcd sfr register list .................................................................88 lcd setup ....................................................................................92 lcd timing and waveforms ....................................................92 blink mode................................................................................93 software controlled blink mode ..........................................93 automatic blink mode ...........................................................93 display element control............................................................93 writing to lcd data registers ..............................................93 reading lcd data registers ..................................................93 voltage generation.......................................................................93 power consumption...............................................................94 contrast control ......................................................................94 lifetime performance.............................................................94 lcd external circuitry..............................................................94 lcd function in psm2..............................................................94 example lcd setup....................................................................95 flash memory ..................................................................................96 flash memory overview............................................................96 flash/ee memory reliability ................................................96 flash memory organization.......................................................96 using the flash memory............................................................97 econflash/ee memory control sfr ............................97 flash functions ......................................................................100 protecting the flash..............................................................100 flash memory timing ...........................................................102 in circuit programming............................................................102 serial downloading ..............................................................102 timers.............................................................................................103 timer sfr register list ................................................................103 timer 0 and timer 1.................................................................106 timer/counter 0 and 1 data registers ..............................106 timer/counter 0 and 1 operating modes ........................106 timer 2 .......................................................................................107 timer/counter 2 data registers.........................................107 timer/counter 2 operating modes ...................................107 pll ..................................................................................................109 pll sfr register list..................................................................109 rtc - real time clock ................................................................111 rtc sfr register list.................................................................111 read and write operations ......................................................114 writing the rtc registers...................................................114 reading the rtc counter sfrs .........................................114 rtc modes ................................................................................114 rtc interrupts ..........................................................................114 interval timer alarm ...........................................................114 rtc calibrationrtc................................................................114 uart serial interface ...................................................................116 uart sfr register list..............................................................116 uart operation modes ...........................................................119 mode 0 (shift register with baud rate fixed at fcore /12) .................................................................................................119 mode 1 (8-bit uart, variable baud rate)........................119
ade7169f16 preliminary technical data rev. prd | page 6 of 140 mode 2 (9- bit uart with baud fixed at f core /64 or f core /32) ................................................................................................. 119 mode 3 (9-bit uart with variable baud rate)............... 120 uart baud rate generation.................................................. 120 mode 0 baud rate generation ........................................... 120 mode 2 baud rate generation ........................................... 120 modes 1 and 3 baud rate generation ............................... 120 timer 1 generated baud rates........................................... 120 timer 2 generated baud rates........................................... 120 uart timer generated baud rates.................................. 121 uart additional features........................................................ 122 enhanced error checking................................................... 122 uart txd signal modulation ........................................... 122 serial peripheral interface interface (spi)................................. 123 spi sfr register list .................................................................. 123 spi pins ...................................................................................... 126 miso (master in, slave out data i/o pin) ...................... 126 mosi (master out, slave in pin)....................................... 126 sclk (serial clock i/o pin)............................................... 126 ss (slave select pin) ............................................................. 126 spi master operating modes.................................................. 126 spi interrupt and status flags ................................................ 127 i 2 c compatible interface ............................................... 129 serial clock generation .......................................................... 129 slave addresses.......................................................................... 129 i2c sfr register list.................................................................. 129 read and write operations .................................................... 130 i2c receive and transmit fifos ........................................... 131 dual data pointers ....................................................................... 132 i/o ports ........................................................................................ 134 parallel i/o ................................................................................ 134 weak internal pullups enabled.......................................... 134 open drain (weak internal pullups disabled) ............... 134 38 khz modulation .............................................................. 134 i/o sfr register list.................................................................. 135 port 0.......................................................................................... 137 port 1.......................................................................................... 138 port 2.......................................................................................... 138 outline dimensions ..................................................................... 139 ordering guide............................................................................. 140
preliminary technical data ade7169f16 rev. prd | page 7 of 140 ade7169f16specifications table 1. (v dd = 3.3 v 5%, agnd = dgnd = 0 v, on-chip reference, xtal = 32.768khz, t min to t max = C40c to +85c) parameter min typ max unit test conditions/comments energy metering measurement accuracy 1 phase error between channels (pf = 0.8 capacitive) 0.05 phase lead 37 (pf = 0.5 inductive) 0.05 phase lag 60 active energy measurement error 2 0.1 % of reading over a dynamic range of 1000 to 1 @25c ac power supply rejection 2 v dd = 3.3 v + 100 mv rms/120 hz output frequency variation 0.01 % i p = v p = 100 mv rms dc power supply rejection 2 v dd = 3.3 v 117 mv dc output frequency variation 0.01 % i p = v p = 100 mv rms active energy measurement bandwidth 1, 2 14 khz reactive energy measurement error 2 0.5 % of reading over a dynamic range of 1000 to 1 @25c vrms measurement error 2 0.5 % of reading over a dynamic range of 100 to 1 @25c vrms measurement bandwidth 1, 2 14 khz irms measurement error 2 0.5 % of reading over a dynamic range of 1000 to 1 @25c irms measurement bandwidth 1, 2 14 khz analog inputs v p C v n , i a C i n and i b C i n maximum signal levels 500 mv peak differential input input impedance (dc) tbd k bandwidth (C3 db) 1 14 khz adc offset error 2 1 mv gain error 2 current channel range = 0.5 v full scale 4 % current channel = 0.5v dc range = 0.25 v full scale 4 % current channel = 0.25v dc range = 0.125 v full scale 4 % current channel = 0.125v dc voltage channel 4 % voltage channel = 0.5v dc gain error match 2 3 % cf1 and cf2 pulse output maximum output frequency 21.1 khz v p -v n = i ap -i n =500mv peak sine wave duty cycle 50 % if cf1 or cf2 frequency > 5.55hz active high pulse width 90 ms if cf1 or cf2 frequency < 5.55hz fault detection fault detection threshold inactive input <> active input 6.25 %, of larger i a or i b active input swap threshold inactive input <> active input 6.25 % of larger i a or i b active accuracy fault mode operation i a active, i b = agnd 0.1 % of reading over a dynamic range of 500 to 1 i b active, i a = agnd 0.1 % of reading over a dynamic range of 500 to 1 fault detection delay 3 seconds swap delay 3 seconds analog peripherals
ade7169f16 preliminary technical data rev. prd | page 8 of 140 parameter min typ max unit test conditions/comments internal adcs (battery, temperature, v dd ) power supply operating range 2.2 3.7 v measured on v swout no missing codes 1 8 bits ac power supply rejection tbd db dc power supply rejection tbd db integral linearity error -1 1 lsb 3 differential linearity error -1 1 lsb conversion delay 4 1 ms temperature sensor accuracy -1 1 c at 25c -4 4 c between -40c and 85c v dcin analog input maximum signal levels 0 v swout v input impedance (dc) 1 m low v dcin detection threshold 1.08 1.2 1.32 v power-on reset (por) v dd por voltage operating range 1 3.7 v detection threshold 1.6 2.9 v por active time-out period tbd ms strobe period in battery operation tbd ms v swout por voltage operating range (v swout ) 1 3.7 v detection threshold 1.8 2.2 v por active time-out period tbd ms v inta and v intd por voltage operating range (v swout ) 1 3.7 v detection threshold 2.25 2.4 v por active time-out period tbd ms battery switch over voltage operating range (v swout ) 2.4 3.7 v v dd ? v bat switching threshold (v swout ) 2.75 tbd v v dd ? v bat switching delay tbd ms v bat ? v dd switching threshold (v dd ) 2.75 tbd v v bat ? v dd switching delay v swout to v bat leakage current tbd 1 ms na lcd C charge pump active lcdvp1 C lcdvp2 charge pump capacitance 200 nf lcdva, lcdvb, lcdvc decoupling capacitance 470 nf lcdva 0 1.7 v lcdvb 0 4.0 v 1/2 bias modes lcdvb 0 3.4 v 1/3 bias modes lcdvc 0 5.1 v 1/3 bias mode lcd stand-by current 100 na 1/2 and 1/3 bias modes v1 segment line voltage lcdva-0.1 lcdva v current on segment line = -2 a v2 segment line voltage lcdvb-0.1 lcdvb v current on segment line = -2 a v3 segment line voltage lcdvc-0.1 lcdvc v current on segment line = -2 a dc voltage across segment and com pin 50 mv lcdvc-lcdvb, lcdvc-lcdva or lcdvb- lcdva lcd C resistor ladder active
preliminary technical data ade7169f16 rev. prd | page 9 of 140 parameter min typ max unit test conditions/comments leakage current 20 na 1/2 and 1/3 bias modes C no load v1 segment line voltage lcdva-0.1v lcdva v current on segment line = -2 a v2 segment line voltage lcdvb-0.1v lcdvb v current on segment line = -2 a v3 segment line voltage lcdvc-0.1v lcdvc v current on segment line = -2 a on-chip reference reference error 12 mv power supply rejection 80 db temperature coefficient 50 ppm/c digital interface logic inputs all inputs except xtal1, xtal2, bctrl, int0 , int1 , reset input high voltage, v inh 2.0 v input low voltage, v inl 0.4 v bctrl, int0 , int1 , reset input high voltage, v inh 1.3 v input low voltage, v inl 0.4 v input currents reset 10 a reset = 0v 100 a reset = v swout = 3.3v port 0, 1 , 2 10 a internal pull-up disabled, input C 0v or v out -250 a internal pull-up enabled, input = 2v, v swout =3.3v -50 a internal pull-up enabled, input = 0.4v, v swout =3.3v input capacitance 10 pf all digital input crystal oscillator crystal equivalent series resistance 30 50 k crystal frequency 32 32.768 33.5 khz xtal1 input capacitance 12 pf xtal2 output capacitance 12 pf mcu clock rate - f core 4.096 mhz crystal = 32.768khz and cd[2:0]=0 32 khz crystal = 32.768khz and cd[2:0]=0b111 logic outputs output high voltage, v oh 2.4 v v dd = 3.3 v 5% i source 80 a output low voltage, v ol 0.4 v v dd = 3.3 v 5% i sink 2 ma floating state leakage current 10 a floating state output capacitance tbd pf startup time 5 at power-on tbd ms from power saving mode 2 (psm2) tbd s from power saving mode 1 (psm1) tbd s power supply inputs v dd 3.0 3.3 3.6 v v bat 2.4 3.3 3.7 v power supply outputs v bat to v swout on-resistance 25 ? v bat = 2.4v v dd to v swout on-resistance 6.1 ? v dd = 3v v swout output current drive 1 ma v inta , v intd 2.25 2.75 v
ade7169f16 preliminary technical data rev. prd | page 10 of 140 parameter min typ max unit test conditions/comments v inta power supply rejection 80 db v intd power supply rejection 60 db power supply currents current in normal mode (psm0) 3.5 ma f core = 4.096 mhz current in normal mode (psm0) 2.1 ma f core = 1.024 mhz current in psm1 with v inta disabled 880 a f core = 1.024 mhz current in psm2 1.5 a 1 these numbers are not production tested but are guaranteed by design and/or characterization data on production release 2 see terminology section for ex planation of specifications. 3 lsb means least significant bit 4 delay between adc conversion request and interrupt set 5 delay between power supply valid and exec ution of first instruction by 8052 core
preliminary technical data ade7169f16 rev. prd | page 11 of 140 timing specifications ac inputs during testing are driven at v swout C 0.5 v for logic 1 and 0.45 v for logic 0. timing measurements are made at v ih min for logic 1 and v il max for logic 0 as shown in figure 2. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs as shown in figure 2. c load for all outputs = 80 pf, unless otherwise noted. v dd = 2.7 v to 3.6 v; all specifications t min to t max , unless otherwise noted. table 2. clock input (external clock driven xtal1) parameter 32.768 khz external crystal min typ max unit t ck xtal1 period 30.52 s t ckl xtal1 width low 6.26 s t ckh xtal1 width high 6.26 s t ckr xtal1 rise time 9 ns t ckf xtal1 fall time 9 ns 1/t core core clock frequency 1 tbd tbd 4.096 mhz 1 ade7129f16 internal pll locks o nto a multiple (512 time s) of the 32.768 khz external crysta l frequency to provide a stable 12. 58 mhz internal clock for the system. the core can operate at this frequency or at a binary submultiple called core_clk, selected via the pllcon sfr. d v dd ? 0.5v 0.45v 0.2dv dd + 0.9v test points 0.2dv dd ? 0.1v v load ? 0.1v v load v load + 0.1v timing reference points v load ? 0.1v v load v load ? 0.1v 04741-0-077 figure 2. timing waveform characteristics
ade7169f16 preliminary technical data rev. prd | page 12 of 140 table 3. i 2 c compatible interface timing parameter parameter min max unit t l sclock low pulse width 1.95 s t h sclock high pulse width 1.95 s t shd start condition hold time tbd s t dsu data setup time tbd s t dhd data hold time tbd s t rsu setup time for repeated start tbd s t psu stop condition setup time tbd s t buf bus free time between a stop condit ion and a start condition tbd s t r rise time of both sclock and sdata 300 ns t f fall time of both sclock and sdata 300 ns t sup 1 pulse width of spike suppressed 50 ns ____________________________________________ 1 input filtering on both the sclock and sdata inputs suppresses noise spikes less than 50 ns. msb t buf sdata (i/o) sclk (i) stop condition start condition repeated start lsb ack msb 1 2-7 8 9 1 s(r) ps t psu t dsu t shd t dhd t sup t dsu t dhd t h t sup t l t rsu t r t r t f t f 04741-0-080 figure 3. i 2 c compatible interface timing
preliminary technical data ade7169f16 rev. prd | page 13 of 140 table 4. spi master mode timing (cpha = 1) parameter min typ max unit t sl sclock low pulse width 1 977 ns t sh sclock high pulse width 1 977 ns t dav data output valid after sclock edge tbd ns t dsu data input setup time befo re sclock edge tbd ns t dhd data input hold time afte r sclock edge tbd ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns ____________________________________________ 1 characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 in powcon sfr set to 0, 0, and 0, respectively, that is, core clock frequency = 4. 096/8 mhz. b. spi bit-rate selection bits spir1 and spr0 in spi2cmod sfr set to 0 and 0, respectively. sclock (cpol = 0) t dsu sclock (cpol = 1) mosi miso msb lsb lsb in bits 6?1 bits 6?1 t dhd t dr t dav t df t sh t sl t sr t sf msb in 04741-0-081 figure 4. spi master mode timing (cpha = 1)
ade7169f16 preliminary technical data rev. prd | page 14 of 140 table 5. spi master mode timing (cpha = 0) parameter min typ max unit t sl sclock low pulse width 1 977 ns t sh sclock high pulse width 1 977 ns t dav data output valid after sclock edge tbd ns t dosu data output setup before sclock edge tbd ns t dsu data input setup time befo re sclock edge tbd ns t dhd data input hold time afte r sclock edge tbd ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns 1 characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 in powcon sfr set to 0, 0, and 0, respectively, that is, core clock frequen cy = 4.096/8 mhz. b. spi bit-rate selection bits spir1 and spr0 in spi2cmod sfr set to 0 and 0, respectively. sclock (cpol = 0) t dsu sclock (cpol = 1) mosi miso msb lsb lsb in bits 6?1 bits 6?1 t dhd t dr t dav t df t dosu t sh t sl t sr t sf msb in 04741-0-082 figure 5. spi master mode timing (cpha = 0)
preliminary technical data ade7169f16 rev. prd | page 15 of 140 table 6. spi slave mode timing (cpha = 1) parameter min typ max unit t ss ss to sclock edge 0 ns t sl sclock low pulse width 977 ns t sh sclock high pulse width 977 ns t dav data output valid after sclock edge tbd ns t dsu data input setup time befo re sclock edge tbd ns t dhd data input hold time afte r sclock edge tbd ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns t dis miso disable after ss rising edge tbd ns t sfs ss high after sclock edge 0 ns 1 miso mosi sclock (cpol = 1) sclock (cpol = 0) ss msb bits 6?1 lsb bits 6?1 lsb in t dhd t dsu t dr t df t dav t sh t sl t sr t sf t sfs msb in t ss t dis figure 6. spi slave mode timing (cpha = 1)
ade7169f16 preliminary technical data rev. prd | page 16 of 140 table 7. spi slave mode timing (cpha = 0) parameter min typ max unit t ss ss to sclock edge 0 ns t sl sclock low pulse width 977 ns t sh sclock high pulse width 977 ns t dav data output valid after sclock edge tbd ns t dsu data input setup time befo re sclock edge tbd ns t dhd data input hold time afte r sclock edge tbd ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns t doss data output valid after ss edge 20 ns t dis miso disable after ss rising edge tbd ns t sfs ss high after sclock edge 0 ns miso mosi sclock (cpol = 1) sclock (cpol = 0) ss bits 6?1 lsb in t dhd t dsu t dr t df t dav t doss t sh t sl t sr t sf t sfs msb in t ss msb bits 6?1 lsb t dis figure 7. spi slave mode timing (cpha = 0)
preliminary technical data ade7169f16 rev. prd | page 17 of 140 table 8. uart timing (shift register mode) parameter 4.09612.58 mhz core_clk variable core_clk min typ max min typ max unit txlxl serial port clock cycle time 2.93 12t core s tqvxh output data setup to clock tbd s tdvxh input data setup to clock tbd s txhdx input data hold after clock tbd s txhqx output data hold af ter clock tbd s set ri or set ti bit 6 t xlxl txd (output clock) rxd (output data) rxd (input data) bit 1 lsb lsb bit 1 bit 6 msb t xhqx t qvxh t dvxh t xhdx 04741-0-086 figure 8. uart timing in shift register mode sclk cs t 1 t 10 t 13 0 0 a4 a5 a3 a2 a1 a0 db0 db7 db0 db7 din dout t 11 t 11 t 12 command byte most significant byte least significant byte t 9 02875-0-083
ade7169f16 preliminary technical data rev. prd | page 18 of 140 absolute maximum ratings t a = 25c, unless otherwise noted. table 9. parameter rating v dd to dgnd C0.3 v to +3.7 v v bat to dgnd C0.3 v to +3.7 v v dcin to dgnd C0.3 v to v swout + 0.3 v input lcd voltage to agnd lcdva, lcdvb, lcdvc 1 C0.3 v to v swout + 0.3 v analog input voltage to agnd v p , v n , i ap , i bpn and i n C2 v to +2 v digital input voltage to dgnd C0.3 v to v swout + 0.3 v digital output voltage to dgnd C0.3 v to v swout + 0.3 v operating temperature range industrial C40c to +85c storage temperature range C65c to +150c junction temperature tbdc 64-lead lqfp, power dissipation tbd ja thermal impedance tbdc/w lead temperature, soldering vapor phase (tbd sec) tbdc infrared (tbd sec) tbdc 64-lead csp, power dissipation tbd ja thermal impedance tbdc/w lead temperature, soldering vapor phase (tbd sec) tbdc infrared (tbd sec) tbdc 1 when used with external resistor divider stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ade7169f16 rev. prd | page 19 of 140 terminology measurement error the error associated with the energy measurement made by the ade7169f16 is defined by the following formula: % 100 re ? ? ? ? ? ? ? ? ? = energy true energy true gister energy error percentage phase error between channels the digital integrator and the high-pass filter (hpf) in the current channel have a non-ideal phase response. to offset this ph ase response and equalize the phase response between channels, two phase-correction networks are placed in the current channel: one for the digital integrator and the other for the hpf. the phase correction networks correct the phase response of the corresponding component a nd ensure a phase match between current channel and voltage channel to within 0.1 over a range of 45 hz to 65 hz with the digita l integrator off. with the digital integrator on, the phase is corrected to within 0.4 over a range of 45 hz to 65 hz. power supply rejection this quantifies the ade7169f16 measurement error as a percentage of reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (3.3 v) is taken. a second reading is obtained with the same input signal levels whe n an ac (100 mv rms/120 hz) signal is introduced onto the supplies. any er ror introduced by this ac signal is expressed as a percentage of readingsee the measurement error definition. for the dc psr measurement, a reading at nominal supplies (3.3 v) is taken. a second reading is obtained with the same input si gnal levels when the supplies are varied 5%. any error introduced is again expressed as a percentage of the reading. adc offset error the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs s till see a dc analog input signal. the magnitude of the offset depends on the gain and input range selectionsee the typical performance characteristics section. however, when hpf1 is switched on, the offset is removed from the current channel and the power calcul ation is not affected by this offset. the offsets can be removed by performing an offset calibrationsee the analog inputs section. gain error the difference between the measured adc output code (minus the offset) and the ideal output codesee the current channel adc an d voltage channel adc sections. it is measured for each of the input ranges on the current channel (0.5 v, 0.25 v, and 0.125 v). the difference is expressed as a percentage of the ideal code.
ade7169f16 preliminary technical data rev. prd | page 20 of 140 pin descriptions table 10. pin function descriptions pin no. mnemonic description 1 com3/ fp27 common output, com3 is used fo r lcd backplane / lcd segment outputs 27 2 com2/ fp28 common output, com2 is used fo r lcd backplane / lcd segment outputs 28 3 com1 common output, com1 is used for lcd backplanes 4 com0 common output, com0 is used for lcd backplanes 5 p1.2/fp25 general-purpose digital i/o / lcd segment outputs 25 6 p1.3/t2ex/fp24 general-purpose digital i/o / timer 2 control input / lcd segment outputs 24 7 p1.4/t2/fp23 general-purpose digital i/o / timer 2 input / lcd segment outputs 23 8 p1.5/fp22 general-purpose digital i/o / lcd segment outputs 22 9 p1.6/fp21 general-purpose digital i/o / lcd segment outputs 21 10 p1.7/fp20 general-purpose digital i/o / lcd segment outputs 20 11 p0.1/fp19 general-purpose digital i/o / lcd segment outputs 19 12 p2.0/fp18 general-purpose digital i/o / lcd segment outputs 18 13 p2.1/fp17 general-purpose digital i/o / lcd segment outputs 17 14 p2.2/fp16 general-purpose digital i/o / lcd segment outputs 16 15 lcdvc output port for lcd levels. this pin should be decoupled with a 470nf capacitor. 16 lcdvp2 this pin is an analog output. a capacitor of 470nf should be connec ted between this pin and lcdvp1 for internal lcd charge pump device. 17, 18 lcdvb, lcdva output ports for lcd levels. thes e pins should be decoupled with a 470nf capacitor. 19 lcdvp1 this pin is an analog output. a capacitor of 470nf should be connec ted between this pin and lcdvp2for internal lcd charge pump device. 35-20 fp0-15 lcd segment outputs 0-15 36 p1.1/txd general-purpose digital i/o / tr ansmitter data output 1 (asynchronous) 37 p1.0/rxd general-purpose digital i/o / receiver data input 1 (asynchronous) 38 p0.7 /ss /t1 general-purpose digital i/o / slave select when spi is in slave mode / timer 1 input 39 p0.6/sclk/t0 general-purpose digital i/o / clock output for i 2 c or spi port / timer 0 input 40 p0.5/miso general-purpose digital i/o / data in for spi port 41 p0.4/mosi/sdata general-purpos e digital i/o / data line i 2 c compatible or data out for spi port 42 p0.3/cf2 general-purpose digital i/o / calibration frequency logic output. the cf2 logic output gives instantaneous active, reactive or apparent power information. 43 p0.2/cf1 general-purpose digital i/o / calibration frequency logic output. the cf1 logic output gives instantaneous active, reactive or apparent power information. 44 sden /p2.3 this pin is used to enable serial download mode when pulled low through a resistor on power-up or reset. on reset this pin will momentarily become an inp ut and the status of the pin is sampled. if there is no pulldown resistor in place, the pin will go momentarilly high and then user code will execute. if a pull-down resistor is in place, the embedded serial download/debug kernel will execute and this pin remains low during internal program execution. this pin can also be used as a general purpose output. 45 bctrl/int1 / p0.0 digital input for battery co ntrol. this logic input connects v dd or v bat to v sw internally when set to logic high or low respectively. when le ft open, the connection between v dd or v bat to v sw is selected internally / external interrupt in put / general-purpose digital i/o 46 xtal2 a crystal can be connected across this pin andxtal1 as described above to provide a clock source for the ade7169f16.the xtal2 pin can drive one cmos load when an external clock is supplied at xtal1 or by the gate oscillator circuit. 47 xtal1 an external clock can be provided at this logic input. alternatively, a parallel resonant at crystal can be connected across xtal1 and xtal2 to provide a cloc k source for the ade7169f16.the clock frequency for specified operation is 32.768 khz. 48 int0 general-purpose digital i/o / interrupt input 49, 50 v p, v n analog inputs for voltage channel. these inputs are fully differentia l voltage inputs with a maximum differential level of 500 mv for specified operation. this ch annel also has an internal pga.
preliminary technical data ade7169f16 rev. prd | page 21 of 140 pin no. mnemonic description 51 ea this pin is used as an input for emulation. when held high, this inp ut enables the device to fetch code from internal program memory locations.the ad e7169f16 does not support external code memory. this pin should not be left floating. 52, 53 i p, i n analog inputs for current channel. these inputs are fully differentia l voltage inputs with a maximum differential level of 500 mv for specified operation. this cha nnel also has an internal pga. 54 agnd this pin provides the ground reference for the analog circuitry 55 i pb analog inputs for second current ch annel. this input is fully differ ential with a maximum differential level of 500 mvrefered to i n for specified operation. this ch annel also has an internal pga. 56 reset reset input, active low 57 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 1.2 v 8% and a typical temperatur e coefficient of 50 ppm/c maximum 58 v bat 3.3v power supply input from battery. th is pin is connected internally to v dd when the battery is selected as the power supply for the ade7169f16. 59 v inta this pin provides access to the on-chip 2.5v anal og ldo. no external active circuitry should be connected to this pin. this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100nf capacitor. 60 v dd 3.3v power supply input from regulator. th is pin is connected internally to v dd when the regulator is selected as the power supply for the ade7169f 16. this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100nf capacitor. 61 v swout 3.3v power supply output from ade7169f16. this pi n provides the supply voltage for the ldos and internal cicuitry of the ade7169f16. th is pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100nf capacitor. 62 v intd this pin provides access to the on-chip 2.5v digi tal ldo. no external active circuitry should be connected to this pin. this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100nf capacitor. 63 dgnd this pin provides the ground reference for the digital circuitry 64 v dcin analog input for dc voltage monito ring. the maximum input voltage on this pin is xxxmv with respect to agnd. this pin is used to moni tor the pre-regulated dc voltage.
ade7169f16 preliminary technical data rev. prd | page 22 of 140 sfr mapping ipsmf strbper batvth scratch1 scratch2 scratch3 scratch4 intpr xf8 table 13 xf9 table 45 xfa table 48 xfb table 17 xfc table 18 xfd table 19 xfe table 20 xff table 12 b diffprog periph batpr rtccomp tempcal xf0 xf3 table 46 xf4 table 15 xf5 table 14 xf6 table 113 xf7 table 114 spimod1 i2cmod spimod2 i2cadr spi2cstat ipsme lcdsege2 vswadc xe8 table 124 table 129 xe9 table 125 table 130 xea table 126 xec table 16 xed table 81 xef table 49 acc wav 1 l wav 1 m wav 1 h wav 2 l wav 2 m wav 2 h xe0 xe2 table 26 xe3 table 26 xe4 table 26 xe5 table 26 xe6 table 26 xe7 table 26 adcgo mirqenl mirqenm mirqenh mirqstl mirqstm mirqsth batadc xd8 table 47 xd9 table 38 xda table 39 xdb table 40 xdc table 35 xdd table 36 xde table 37 xdf table 50 psw vrmsl vrmsm vrmsh irmsl irmsm irmsh tempadc xd0 table 53 xd1 table 26 xd2 table 26 xd3 table 26 xd4 table 26 xd5 table 26 xd6 table 26 xd7 table 51 t2con rcap2l rcap2h tl2 th2 xc8 table 96 xca table 104 xcb table 103 xcc table 102 xcd table 101 wdcon kyreg powcon eadrl eadrh xc0 table 65 xc1 table 106 xc5 table 21 xc6 table 91 xc7 table 92 ip econ flshky protky edata protb0 protb1 protr xb8 table 63 xb9 table 84 xba table 85 xbb table 86 xbc table 87 xbd table 88 xbe table 89 xbf table 90 lcdcony pinmap0 pinmap1 pinmap2 xb1 table 74 xb2 table 135 xb3 table 136 xb4 table 137 ie ieip2 lcdptr lcddat cfg xa8 table 62 xa9 table 64 xac table 79 xae table 80 xaf table 58 p2 timecon hthsec sec min hour intval dpcon xa0 table 140 xa1 table 107 xa2 table 108 xa3 table 109 xa4 table 110 xa5 table 111 xa6 table 112 xa7 table 132 scon sbuf spi2ctx spi2crx lcdcon x sbaudf sbaudt epcfg x98 table 116 x99 table 117 x9a table 122 x9b table 123 x9c table 72 x9d table 119 x9e table 118 x9f table 134 p1 maddpt mdatl mdatm mdath lcdcon lcdclk lcdsege x90 table 139 x91 table 26 x92 table 26 x93 table 26 x94 table 26 x95 table 71 x96 table 75 x97 table 78 tcon tmod tl0 tl1 th0 th1 x88 table 95 x89 table 94 x8a table 98 x8b table 100 x8c table 97 x8d table 99 p0 sp dpl dph pcon x80 table 138 x81 table 57 x82 table 55 x83 table 56 x87 table 54 mnemonic wdcon xc0 table 65 mapkey address link to detailed table
preliminary technical data ade7169f16 rev. prd | page 23 of 140 power management the ade7169f16 has an elaborate power management circuitry that manages the regular power supply to battery switch over and power supply failures. the power management functionalities can be accessed directly through the 8052 sfr C see table 11. table 11. power management sfrs sfr address (hex) r/w name description 0xec r/w ipsme power management interrupt enable 0xf5 r/w batpr battery switchover configuration 0xf8 r/w ipsmf power management interrupt flag 0xff r/w intpr interrupt wake-up configuration power management register details table 12. interrupt pins configuration sfr (intpr, 0xff) bit location bit mnemonic default value description 7 rtccal 0 control rtc calibration output when set uncalibrated clock at 1 hz is output on cf1 pin. 6-4 reserved controls the function of int1 t int1prg[2:0] function x 0 0 gpio x 0 1 bctrl 0 1 x int1 input disabled 3-1 int1prg[2:0] 000 1 1 x int1 input enabled controls the function of int0 int0prg function 0 int0 input disabled 0 int0prg 0 1 int0 input enabled table 13. power management interrupt flag sfr (ipsmf, 0xf8) bit location bit addr. bit name default value description 7 0xff fpsr 0 power supply restored interrupt flag. set when the v dd power supply has been restored. this occurs when the source of v sw changes from v bat to v dd . 6 0xfe fpsm 0 psm interrupt flag. set when an enabled psm interrupt condition occurs. 5 0xfd fsag 0 voltage sag interrupt flag. set when an ade energy meas urement sag condition occurs. 4 0xfc reserved 0 this bit must be kept cleared for proper operation 3 0xfb fvsw 0 v sw monitor interrupt flag. set when v sw changes by vswdif or when v sw measurement is ready. 2 0xfa fbat 0 v bat monitor interrupt flag. set when v bat falls below batvth or when the v bat measurement is ready. 1 0xf9 fbso 0 battery sw itchover interrupt flag.
ade7169f16 preliminary technical data rev. prd | page 24 of 140 set when v sw switches from v dd to v bat. 0 0xf8 fvdc 0 v dcin monitor interrupt flag. set when v dcin falls below 1.2v. table 14. battery switchover configuration sfr (batpr, 0xf5) bit location bit mnemonic default value description 7-2 reserved 00 these bits must be kept to 0 for proper operation control bits for battery switchover. batprg [1:0] function 0 0 battery swichover enabled on low v dd 0 1 battery swichover enabled on low v dd and low v dcin 1-0 batprg [1:0] 00 1 x battery switchover disabled table 15. peripheral configuration sfr (periph, 0xf4) bit location bit mnemonic default value description 7 rxflag 0 if set, indicates that a rx edge event triggered wakeup from psm2 indicates the power supply that is connected internally to v sw . 0 v sw =v bat 6 vswsource 1 1 v sw =v dd 5 vdd_ok 1 if set, indicates that vdd power supply is ok for operation 4 pll_flt 0 if set, indica tes that pll is not locked 3 ref_bat_en 0 if set, internal voltage refe rence enabled in psm2 mode. this bit should be set if lcd on in psm2 mode. 2 reserved 0 this bit should be kept to zero controls the function of the p1.0/rx pin. rxprog [1:0] function 0 0 gpio 0 1 rx with wakeup disabled 1-0 rxprog[1:0] 00 1 1 rx with wakeup enabled table 16. power management interrupt enable sfr (ipsme, 0xec) bit location bit mnemonic default value description 7 epsr 0 enables a psm interrupt when th e power supply restored flag is set. 6 adeiautclr 0 if set, the ade interrupt status regi sters mirqsth/m/l registers will be read with reset. 5 esag 0 enables a psm interrupt when the voltage sag flag (fsag) is set. 4 reserved 0 this bit must be kept cleared for proper operation 3 evsw 0 enables a psm interrupt when the v sw monitor flag (fvsw) is set. 2 ebat 0 enables a psm interrupt when the v bat monitor flag (fbat) is set. 1 ebso 0 enables a psm interrupt when the battery switchover flag (fbso) is set. 0 evdcin 0 enables a psm interrupt when the v dcin monitor flag (fvdcin) is set. table 17. scratch pad 1 sfr (scratch1, 0xfb) bit location bit mnemonic default value description 7-0 scratch1 0 value can be written/read in this register. this value will be maintained in all the power saving modes of the ade7169f16
preliminary technical data ade7169f16 rev. prd | page 25 of 140 table 18. scratch pad 2 sfr (scratch2, 0xfc) bit location bit mnemonic default value description 7-0 scratch2 0 value can be written/read in this register. this value will be maintained in all the power saving modes of the ade7169f16 table 19. scratch pad 3 sfr (scratch3, 0xfd) bit location bit mnemonic default value description 7-0 scratch3 0 value can be written/read in this register. this value will be maintained in all the power saving modes of the ade7169f16 table 20. scratch pad 4 sfr (scratch4, 0xfe) bit location bit mnemonic default value description 7-0 scratch4 0 value can be written/read in this register. this value will be maintained in all the power saving modes of the ade7169f16 table 21. power control sfr (powcon, 0xc5) bit location bit mnemonic default value description 7-5 reserved 0 4 coreoff 0 set this bit to shut down the core if in the psm1 operating mode. 3 reserved controls the core clock frequency, f core . f core =4.096mhz/2 cd cd[2:0] f core (mhz) 0 0 0 4.096 0 0 1 2.048 0 1 0 1.024 0 1 1 0.512 1 0 0 0.256 1 0 1 0.128 1 1 0 0.064 2-0 cd[2:0] 010 1 1 1 0.032 note: writing data to the powcon sfr involves a double instruction sequence. global interrupts must first be disabled to ensure that the two instructions occur consecutively. the kyreg sfr is set to 0xa7 and immediately followed by a write to the powcon sfr. f or example: clr ea ;disable interrupts while configuring to wdt mov kyreg,#0a7h ;write kyreg to 0xa7 to get write access to the powcon sfr mov powcon, #10h ;shutdown the core nop nop power supply architecture ade7169f16 has two power supply inputs, v dd and v bat , and requires only a single 3.3v power supply at v dd for full operation. a battery backup, or secondary power supply, with a maximum of 3.6v can be connected to the v bat input. internally, the ade7169f16 connects v dd or v bat to v sw , which is used to derive the power for the ade7169f16 circuitry. the
ade7169f16 preliminary technical data rev. prd | page 26 of 140 v swout output pin reflects the voltage at v sw , and has a maximum output current of tbd ma. this pin may also be used to power a limited number of peripheral components. the 2.5v analog supply, v inta and the 2.5v supply for the core logic, v intd , are derived by on-chip linear regulators from v sw . figure 9 shows the power supply architecture of ade7169f16. the ade7169f16 provides automatic battery switchover between v dd and v bat based on the voltage level detected at v dd or v dcin . additionally, the bctrl input can also be used to trigger a battery switchover. the conditions for switching v sw from v dd to v bat and back to v dd are described in the battery switchover section. v dcin is an input pin that can be connected to a 0v to 3.3v dc signal. this input is intend ed for power supply supervisory purposes and does not provide power to the ade7169f16 circuitry - see battery switchover section. mcu scratchpad lcd rtc temperature adc dcin v dd v intd v inta v 3.3v 2.5v ldo bat v swout v bctrl sw v ade spi/i2c uart ldo power supply management adc adc figure 9: power supply architecture battery switchover ade7169f16 monitors v dd , v bat , and v dcin . automatic battery switchover from v dd to v bat can be configured based on the status of v dd , v dcin , or the bctrl pin. battery switchover is enabled by default. setting bit 1 in the battery switchover configuration sfr (batpr, 0xf5), disables battery switchover so that v dd is always connected to v sw . the source of v sw is indicated by bit 6 in the peripheral configuration sfr (periph, 0xf4), which is set when v sw is connected to v dd and cleared when v sw is connected to v bat . the battery switchover functionality provided by the ade7169f16 allows a seamless transition from v dd to v bat . an automatic battery switchover option ensures a stable power supply to the ade7169f16, as long as the external battery voltage is above tbd v. it allows continuous code execution even while the internal power supply is switching from v dd to v bat and back. note that the energy metering adcs are not available when v bat is being used for v sw . power supply monitor (psm) interrupts can be enabled to indicate when battery switchover occurs and when the v dd power supply is restored - see the power supply monitor interrupt (psm) section. switching from v dd to v bat there are three events that can be enabled to switch the internal power supply, v sw , from v dd to v bat : 1. (v dcin < 1.2 v): when v dcin falls below 1.2v v sw switches from v dd to v bat . this event is enabled when the battprog[1:0] bits in the battery switchover configuration sfr (batpr, 0xf5) are clear. setting this bit will disable switchover based on v dcin . battery switchover on low v dcin is disabled by default. 2. (v dd < tbd v): when v dd falls below tbd v v sw switches from v dd to v bat . this event is enabled when battprog[1] in the battery switchover configuration sfr (batpr, 0xf5) is cleared. 3. rising edge on bctrl: when the battery control pin, bctrl, goes high, v sw switches from v dd to v bat . this external switchover signal can trigger a switchover to v bat at any time. setting bits int1prg[4:2] to 0bx01 in the interrupt pins configuration sfr (intpr, 0xff) enables the battery control pin. switching from v bat to v dd to switch v sw back from v bat to v dd all of the events that are enabled to force battery switchover must be false: 1. (v dcin < 1.2 v) and (v dd < tbd v) enabled: if the low v dcin condition is enabled, v sw switches to v dd after v dcin remains above tbd v for tbd seconds and v dd remains above tbd v for tbd seconds. 2. (v dd < tbd v) enabled: v sw switches back to v dd after v dd has been above tbd v for tbd seconds. 3. bctrl enabled: v sw switches back to v dd after bctrl is low and number 1 or number 2 are satisfied. power supply monitor interrupt (psm) the power supply monitor interrupt (psm) alerts the 8052 core of power supply events. the psm interrupt is disabled by default. setting the epsm bit in the interrupt enable and priority 2 sfr (ieip2, 0xa9) enables the psm interrupt. the power management interrupt enable sfr (ipsme, 0xec) controls the events that result in a psm interrupt. figure 10 is a diagram illustrating how the psm interrupt vector is shared among the psm interrupt sources. the psm interrupt flags are latched and must be cleared by writing to the flag register.
preliminary technical data ade7169f16 rev. prd | page 27 of 140 epsr esag ebat ebso evdcin fpsr fsag fbat fbso fvdcin fpsm ipsme addr. 0ech ipsmf addr. 0f8h eti epsm esi pti psi ieip2 addr. 0a9h adeautoclr epsr esag ebat evsw ebso fpsr fsag fbat fvsw fbso fpsm pending psm interrupt epsm true? evsw reserved reserved reserved reserved eade : not involved in psm interrupt signal chain fvsw evdcin fvdcin figure 10: psm interrupt sources battery switchover and power supply restored psm interrupt the ade7169f16 can be configured to generate a psm interrupt when the source of v sw changes from v dd to v bat , indicating battery switchover. setting the ebso bit in the power management interrupt enable sfr (ipsme, 0xec) enables this event to generate a psm interrupt. the ade7169f16 can also be configured to generate an interrupt when the source of v sw changes from v bat to v dd , indicating that the v dd power supply has been restored. this event is enabled to generate a psm interrupt by setting the epsr bit in the power management interrupt enable sfr (ipsme, 0xec). the flags in the power management interrupt flag sfr (ipsmf, 0xf8) for these interrupts, bsof and psrf are set regardless of whether the respective enable bits have been set. the battery switchover and power supply restore event flags, bsof and psrf, are latched. these events must be cleared by writing a zero to these bits. bit 6 in the peripheral configuration sfr (periph, 0xf4), vswsource, tracks the source of v sw . the bit is set when v sw is connected to v dd and cleared when v sw is connected to v bat . v sw monitor psm interrupt the ade7169f16 can be configured to generate a psm interrupt when v sw changes magnitude by more than a configurable threshold. this threshold is set in the temperature and supply delta sfr (diffprog, 0xf3) Csee supply voltage measurement section. setting the evsw bit in the power management interrupt enable sfr (ipsme, 0xec) enables this event to generate a psm interrupt. the v sw voltage is measured using a dedicated adc. these measurements take place in the background at intervals to check the change in v sw . conversions can also be initiated by writing to the start adc measurement sfr (adcgo, 0xd8). the evsw flag will indicate that a v sw measurement is ready. see the supply voltage measurement section for details on how v sw is measured. v bat monitor psm interrupt the v bat voltage is measured using a dedicated adc. these measurements take place in the background at intervals to check the change in v bat . the battf bit is set when the battery level is lower than the threshold set in the battery detection threshold sfr (batvth, 0xfa) or when a new measurement is ready in the battery adc value sfr (batadc, 0xdf) - see battery measurement section. setting the ebatt bit in the power management interrupt enable sfr (ipsme, 0xec) enables this event to generate a psm interrupt. v dcin monitor psm interrupt the v dcin voltage is monitored by a comparator. the fvdc bit in the power management interrupt flag sfr (ipsmf, 0xf8) is set when the v dcin input level is lower than 1.2 v. setting the evdcin bit in the power management interrupt enable sfr
ade7169f16 preliminary technical data rev. prd | page 28 of 140 (ipsme, 0xec) enables this event to generate a psm interrupt. this event associated with the sag monitoring can be used to detect a power supply - v dd - being compromised and trigger further actions prior to decide a switch of v dd to v bat . sag monitor psm interrupt the ade7169f16 energy measurement dsp monitors the ac voltage input at the v p and v n input pins. the saglvl register is used to set the threshold for a line voltage sag event. the sagf bit in the power management interrupt flag sfr (ipsmf, 0xf8) is set if the line voltage stays below the level set in the saglvl register for the number of line cycles set in the sagcyc register, - see line voltage sag detection section. setting the esag bit in the power management interrupt enable sfr (ipsme, 0xec) enables this event to generate a psm interrupt. using the power supply features in an energy meter application, v dd , the 3.3v power supply, is typically generated from the ac line voltage and regulated to 3.3v by a voltage regulator ic. the pre-regulated dc voltage, typically 5v to 12v, can be connected to v dcin through a resistor divider. a 3.6v battery can be connected to v bat . figure 11 shows how the ade7169f16 power supply inputs would be set up in this application. bctrl voltage supervisory voltage supervisory ac input sag detection psu 3.3v regulator 5 - 12v dc power supply management (240, 220, 110v typical) v dcin v dd v swout v bat v p v n ipsmf sfr (addr. 0xf8) v sw figure 11. power supply management for energy meter application figure 12 shows the sequence of events that will be generated for the power meter application in figure 11 if the main power supply generated by the psu starts to fail. the sag detection can provide the earliest warning of a potential problem on v dd . when a sag event occurs, the user code can be configured to backup data and prepare for battery switchover if desired. the relative spacing of these interrupts will depend on the design of the power supply. figure 13 shows the sequence of events that will be generated for the power meter application shown in figure 11 if the main power supply starts to fail, with battery switchover on low v dcin or low v dd enabled.
preliminary technical data ade7169f16 rev. prd | page 29 of 140 v - v pn v dcin v dd sag level trip point 2.75v sag event (fsag=1) vevent 1.2v dcin sagcyc=1 automatic battery switchover v connected to v sw bat if switchover on low v is enabled, dd bso event (fbso=1) (fvdc=1) t 1 t 2 figure 12: power supply management interr upts and battery switchover with only v dd enabled for battery switchover bso event (fbso=1) v - v pn v dcin v dd sag level trip point 2.75v sag event (fsag=1) v event 1.2v dcin sagcyc=1 automatic battery switchover v connected to v sw bat if switchover on low v is enabled, dcin (fvdc=1) t 1 t 3 figure 13: power supply management interrupts and battery switchover with v dd or v dcin enabled for battery switchover time comment t 1 tbd time between when v dcin goes below 1.2 v and when vswf is raised. t 2 tbd time between when v dd falls below tbd v and when battery switchover occurs. t 3 tbd time between when v dcin falls below 1.2 v and when battery switchover occurs, if v dcin is enabled to cause battery switchover. vdcin_opt[1:0] in the battery switchover configuration sfr (batpr, 0xf5) sets this timeout table 22: power supply event timings operating modes
ade7169f16 preliminary technical data rev. prd | page 30 of 140 finally, the transition between v dd and v bat and the different power supply modes (see operating modessection) is represented in figure 15. v - v pn v dcin 1.2v sag level trip point v dd v bat 2.75v sag event v dcin event 30ms min. v sw battery switch enabled on low v dcin v sw battery switch enabled on low v dd v dcin event 30ms min. psm0 psm0 psm0 psm0 psm1 or psm2 psm1 or psm2 figure 14: power supply management transitions between modes
preliminary technical data ade7169f16 rev. prd | page 31 of 140 operating modes psm0 (normal mode) in psm0, normal operating mode, v sw is connected to v dd . all of the analog and digital circuitries powered by v intd and v inta are enabled by default. the default clock frequency for psm0, f core , established during a power-on-reset or software reset, is tbd mhz. psm1 (battery mode) in psm1, v sw is connected to v bat . in this operating mode, the 8052 core and all of the digital circuitry are enabled by default. the analog circuitry for the ade energy metering dsp powered by v inta is disabled. this analog circuitry will automatically start up again once the v dd supply is above tbd v if the pwrdn bit in the mode1 register (0x0b) is cleared. the default f core for psm1, established during a power-on-reset or software reset, is 1.024 mhz. psm2 (sleep mode) psm2 is a low power consumption sleep mode for use in battery operation. in this mode, v sw is connected to v bat . all of the 2.5v digital and analog circuitry powered through v inta and v intd is disabled, including the mcu core, resulting in the following: 1. the ram in the mcu is no longer valid. 2. the program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5v supply is shut down. therefore, the program will not resume from where it left off but will always start from the power on reset vector when the ade7169f16 comes out of psm2. the 3.3v peripherals temperature adc, v bat adc, v sw adc, rtc and lcd are active in psm2. they can be enabled or disabled to reduce power consumption and are configured for psm2 operation when the mcu core is activesee the individual peripherals for more information on their psm2 configuration. the ade7169f16 remains in psm2 until an event occurs to wake it up. in psm2, the ade7169f16 provides 4 scratch pad ram sfr that are maintained during this mode. these sfrs can be used to save data from psm0 or psm1 modes when entering psm2 modes - see table 16 to table 20. in psm2, the ade7169f16 maintains some sfrs C see table 23. the sfrs that are not listed in this table should be restored when the part enters psm0 or psm1 frm psm2 mode. table 23. sfr maintained in psm2 i/o configuration power supply monitoring interrupt pins configuration sfr (intpr, 0xff) peripheral configuration sfr (periph, 0xf4) port 0 weak pull-up enable sfr (pinmap0, 0xb2) port 1 weak pull-up enable sfr (pinmap1, 0xb3) port 2 weak pull-up enable sfr (pinmap2, 0xb4) scratch pad 1 sfr (scratch1, 0xfb) scratch pad 2 sfr (scratch2, 0xfc) scratch pad 3 sfr (scratch3, 0xfd) scratch pad 4 sfr (scratch4, 0xfe) battery detection threshold sfr (batvth, 0xfa) battery switchover configuration sfr (batpr, 0xf5) battery adc value sfr (batadc, 0xdf) peripheral adc strobe period sfr (strbper, 0xf9) temperature and supply delta sfr (diffprog, 0xf3) vsw adc value sfr (vswadc, 0xef) temperature adc value sfr (tempadc, 0xd7) peripherals C rtc peripherals - lcd rtc nominal compensation sfr (rtccomp, 0xf6) rtc temperature compensation sfr (tempcal, 0xf7) rtc configuration sfr (timecon, 0xa1) hundredths of a second counter sfr (hthsec, 0xa2) seconds counter sfr (sec, 0xa3) minutes counter sfr (min, 0xa4) hours counter sfr (hour, 0xa5) alarm interval sfr (intval, 0xa6) lcd segment enable 2 sfr (lcdsege2, 0xed) lcd configuration y sfr (lcdcony, 0xb1) lcd configuration x sfr (lcdconx, 0x9c) lcd configuration sfr (lcdcon, 0x95) lcd clock sfr (lcdclk, 0x96) lcd segment enable sfr (lcdsege, 0x97)
ade7169f16 preliminary technical data rev. prd | page 32 of 140 3.3v peripherals and wakeup events some of the 3.3v peripherals are capable of waking the ade7169f16 from psm2. the events that can cause the ade7169f16 to wake from psm2 are listed in the wakeup events column in table 24. table 24. 3.3v peripherals and wakeup events 3.3v peripheral wakeup event wakeup enable bits flag interrupt vector comments temperature adc t maskable - itadc the temperature adc can wake-up the 8052 if the itadc flag is set . this fl ag is set according to the description in the temperature measurement section. this wakeup event can be disabled by disabling temperature measurements in the temperature and supply delta sfr (diffprog, 0xf3) in psm2. v sw adc v maskable vswf ipsm the v sw measurement can wake-up the 8052. the vswf is set according to the description in the supply voltage measurement section. this wakeup event can be disabled by clearing the evsw in the power management interrupt enable sfr (ipsme, 0xec). power supply management psr non- maskable psr ipsm the 8052 will wake up if the power supply is restored (if v sw switches to be connected to v dd ). the vswsource flag, bit 6 of the peripheral configuration sfr (periph, 0xf4) sfr, is set to indicate that v sw is connected to v dd . this is a nonmaskable wakeup event. midnight non- maskable midnight irtc the ade7169f16 will wake up at midnight every day to update its calendar. this event is a nonmaskable wakeup event. rtc alarm maskable alarm irtc set an alarm to wake the ade7169f16 after the desired amount of time. the rtc alarm is enabled by setting the alarm bit in the rtc configuration sfr (timecon, 0xa1). all i/o pins are treated as inputs. the weak pull-up on each i/o pin can be disabled individually in the port 0 weak pull- up enable sfr (pinmap0, 0xb2), port 1 weak pull-up enable sfr (pinmap1, 0xb3 ) and port 2 weak pull-up enable sfr (pinmap2, 0xb4) to decrease current consumpt ion. the interrupts can be enabled/disabled. int0 int0prog =1 - ie0 the edge of the interrupt is selected by tcon.it0 the ie0 flag bit in the tcon register will not be affected. int1 int1prog [2:0 ]= 11x - ie1 the edge of the interrupt is selected by tcon.it1 the ie1 flag bit in the tcon register will not be affected. i/o ports rx edge rxprog [1:0] = 11 periph.7 (rxfg) - an rx edge event will occur if a rising or falling edge is detected on the rx line external reset reset non- maskable - - if the reset pin is brought low while the ade7169f16 is in psm2, it will wake up to psm1. lcd - - - - the lcd can be enabled/disabl ed in psm2. the lcd data memory will remain intact. scratchpad - - - - the 4 scratchx registers will remain intact in psm2. transitioning between operating modes the operating mode of the ade7169f16 is determined by the power supply connected to v sw . therefore a change in the power supply such as when v sw switches from v dd to v bat or when v sw switches to v dd changes the operating mode. this section describes events that change the operating mode. automatic battery switchover (psm0 to psm1) if any of the enabled battery switchover events occur (see the battery switchover section), v sw switches to v bat . this switchover results in a transition from the psm0 to psm1 operating mode. when battery switchover occurs, the analog circuitry used in the ade energy measurement dsp is disabled.
preliminary technical data ade7169f16 rev. prd | page 33 of 140 to reduce power consumption, the user code can initiate a transition to psm2. entering sleep mode (psm1 to psm2) to reduce power consumption when v sw is connected to v bat , user code can initiate sleep mode, psm2, by setting bit 4 in the power control sfr (powcon, 0xc5) to shut down the mcu core. events capable of waking the mcu can be enabledsee the 3.3v peripherals and wakeup events section. servicing wakeup events (psm2 to psm1) the ade7169f16 may need to wake up from psm2 to service wakeup events C see the 3.3v peripherals and wakeup events section. psm1 code execution will begin at the power on reset vector. after servicing the wakeup event, the ade7169f16 can return to psm2 by setting bit 4 in the power control sfr (powcon, 0xc5) to shut down the mcu core. automatic switch to v dd (psm2 to psm0) if the conditions to switch v sw from v bat to v dd occur (see the battery switchover section), the operating mode will switch to psm0. when this switch occurs, the mcu core and the analog circuitry used in the ade energy measurement dsp will start up again automatically. psm0 code execution will begin at the power on reset vector. automatic switch to v dd (psm1 to psm0) if the conditions to switch v sw from v bat to v dd occur (see the battery switchover section), the operating mode will switch to psm0. when this switch occurs, the analog circuitry used in the ade energy measurement dsp will start up automatically. note that code execution will continue normally. a software reset can be performed to start psm0 code execution at the power on reset vector. using the power management features since program flow is different for each operating mode, the status of v sw must be known at all times. the vswflag bit in the power management interrupt flag sfr (ipsmf, 0xf8) indicates what v sw is connected to. this bit can be used to control program flow on wakeup. since code execution always starts at the power on reset vector, bit 6 of the peripheral configuration sfr (periph, 0xf4) can be tested to determine which power supply is being used and to branch to normal code execution or to wakeup event code execution. power supply events can also occur when the mcu core is active. to be aware of events that change what v sw is connected to: ? enable the battery switchover interrupt (evsw) if v sw =v dd at power up. ? enable the power supply restored interrupt (epsr) if v sw =v bat at power up. an early warning that battery switchover is about to occur is provided by sag detection and possibly low v dcin detection see the battery switchover section. for a user controlled battery switchover, enable automatic battery switchover on low v dd only. then enable the low v dcin event to generate the psm interrupt. when a low v dcin event occurs, start data backup. upon completion of the data backup, enable battery switchover on low v dcin . then battery switchover will occur tbdms later. psm0 normal mode v sw connected to v dd psm1 battery mode v sw connected to v bat psm2 sleep mode v sw connected to v bat user code directs mcu to shutdown core after servicing wakeup event automatic battery switchover power supply restored wakeup event power supply restored figure 15: transitioning between operating modes
preliminary technical data ade7169f16 rev. prd | page 34 of 140 energy measurement the ade7169f16 provides a fixed function energy measurement digital processing core that provides all the information needed to measure energy in a single phase energy meters. the ade7169f16 provides two ways to access the energy measurements: direct access through sfr for time sensitive information and indirect access through address and data sfr registers for the majority of the energy measurements. the irms, vrms, interrupts and waveform registers are readily available through sfrs as shown in table 25. other energy measurement information is mapped to a page of memory that is accessed indirectly through. the address and data registers act as pointers to the energy measurement internal registers. access to energy measurement sfr access to the energy measurement sfrs is achieved by reading or writing to the sfr addresses detailed in table 26. the internal data for the mirqx sfrs are latched byte by byte into the sfr when the sfr is read. the wav1x, wav2x, vrmsx and irmsx registers are all 3 bytes sfrs. the 24-bit data is latched into these sfrs when the high byte is read. reading the low or medium byte before the high byte results in reading the date from the previous latched sample. sample 8051 code to read the vrms register is shown below: mov r1, vrmsh //latches data in vrmsh, vrmsm and vrmsl sfr mov r2, vrmsm mov r3, vrmsl access to internal energy measurement registers access to the internal energy measurement registers is achieved by writing to the energy measurement pointer address (sfr address 91h). the maddpt register selects the energy measurement register to be accessed and determines if a read or a write is performedsee table 25. table 25. energy measurement pointer address sfr (maddpt, 0x91) bit 7 6 5 4 3 2 1 0 description 1: write 0: read energy measurement internal register address writing to internal energy measurement registers when bit7 of maddpt sfr is set, the content of the mdata sfrs (mdatl, mdatm and mdath) is transferred to the internal energy measurement register designated by the address in maddpt sfr. if the internal register is one byte long, only mdatl sfr content is copied to the internal register while mdatm and mdath sfr contents are ignored. the energy measurement core functions with an internal clock of 4.096 mhz/5 or 819.2 khz. as the 8052 core functions with another clock, 4.096mhz / 2 cd , synchronization between the two clock environments when cd = 0 or 1 is an issue. when data is written to the internal energy measurement a small wait period need to be implemented before another read or write to these registers is implemented. sample 8051 code to write 0x0155 to the two bytes saglvl register, located at 14h in the energy measurement memory space is shown below: mov mdatm,#01h mov mdatl,#55h mov maddpt,#saglvl_w (address 0x94) mov a, #05h djnz acc, $ ;next write or read to energy measurement sfr can be done after this. reading internal energy measurement registers when bit7 of maddpt sfr is cleared, the content of the internal energy measurement register designated by the address in maddpt is transferred to the mdata sfrs (mdatl, mdatm and mdath). if the internal register is one byte long, only the mdatl sfr content is updated with a new value while mdatm and mdath sfr content are reset to 00h. the energy measurement core functions with an internal clock of 4.096 mhz/5 or 819.2 khz. as the 8052 core functions with another clock, 4.096mhz / 2 cd , synchronization between the two clock environments when cd = 0 or 1 is an issue. when data is read from the internal energy measurement, a small wait period need to be implemented before the mdatx sfrs are transferred to another sfr. sample 8051 code to read the peak voltage in the 2-byte vpklvl register, located at 0x16, into the data pointer is shown below: mov maddpt,#vpklvl_r (address 0x16) mov a, #05h djnz acc, $ mov dph, mdatm mov dpl, mdatl
preliminary technical data ade7169f16 rev. prd | page 35 of 140 table 26. energy measurement sfrs sfr address (hex) r/w name description 0x91 r/w maddpt energy measurement pointer address 0x92 r/w mdatl energy measurement pointer data lsbyte 0x93 r/w mdatm energy measurement pointer data middle byte 0x94 r/w mdath energy measurement pointer data msbyte 0xd1 r vrmsl vrms measurement lsbyte 0xd2 r vrmsm vrms measurement middle byte 0xd3 r vrmsh vrms measurement msbyte 0xd4 r irmsl irms measurement lsbyte 0xd5 r irmsm irms measurement middle byte 0xd6 r irmsh irms measurement msbyte 0xd9 r/w mirqenl energy measurement interrupt enable lsbyte 0xda r/w mirqenm energy measurement interrupt enable middle byte 0xdb r/w mirqenh energy measurement interrupt enable msbyte 0xdc r/w mirqstl energy measurement interrupt status lsbyte 0xdd r/w mirqstm energy measurement interrupt status middle byte 0xde r/w mirqsth energy measurement interrupt status msbyte 0xe2 r wav1l selection 1 sample lsbyte 0xe3 r wav1m selection 1 sample middle byte 0xe4 r wav1h selection 1 sample msbyte 0xe5 r wav2l selection 2 sample lsbyte 0xe6 r wav2m selection 2 sample middle byte 0xe7 r wav2h selection 2 sample msbyte energy measurement registers table 27. energy measurement register list address maddpt[6:0] name r/w length signed /unsigned default value description 0x00 reserved - - - - - 0x01 watthr r 24 s 0 read watt-ho ur accumulator without reset 0x02 rwatthr r 24 s 0 read watt- hour accumulator with reset 0x03 lwatthr r 24 s 0 read watt-hour accumulator synchronous to line cycle
ade7169f16 preliminary technical data rev. prd | page 36 of 140 address maddpt[6:0] name r/w length signed /unsigned default value description 0x04 varhr r 24 s 0 read var-ho ur accumulator without reset 0x05 rvarhr r 24 s 0 read var-hour accumulator with reset 0x06 lvarhr r 24 s 0 read var-hour a ccumulator synchronous to line cycle 0x07 vahr r 24 s 0 read va-hour accumulator without reset 0x08 rvahr r 24 s 0 read va-hour accumulator with reset 0x09 lvahr r 24 s 0 read va-hour accu mulator synchronous to line cycle 0x0a per_freq r 16 u 0 read line period or frequency register depending on mode2 register 0x0b mode1 r/w 8 u 0x06 set basic configuration of energy measurement C see table 28 0x0c mode2 r/w 8 u 0x40 set basic configuration of energy measurement C see table 29 0x0d wavmode r/w 8 u 0 set configuration of waveform sample 1 and waveform sample 2 C see table 30 0x0e nlmode r/w 8 u 0 set level of en ergy no-load thresholds - table 31 0x0f accmode r/w 8 u 0 set configuration of watt, var accumulation and various tamper alarms C see table 32 0x10 phcal r/w 8 s 0x40 set phase calibration register C see phase compensation section 0x11 zxtout r/w 12 0x0fff set time out for zero-crossi ng time out detection C see zero-crossing timeout 0x12 lincyc r/w 16 u 0xffff set number of half line cycles for lwatthr, lvarhr and lvahr accumulators 0x13 sagcyc r/w 8 u 0xff set number of half line cycles for sag detection C see line voltage sag detection 0x14 saglvl r/w 16 u 0 set detection level for sag detection - see line voltage sag detection 0x15 ipklvl r/w 16 u 0xffff set peak detection level for current peak detection C see peak detection 0x16 vpklvl r/w 16 u 0xffff set peak detection level for voltage peak detectionC see peak detection 0x17 ipeak r 24 u 0 read current peak level without reset C see peak detection 0x18 rstipeak r 24 u 0 read current peak level with reset C see peak detection 0x19 vpeak r 16 u 0 read voltage peak level without reset C see peak detection 0x1a rstvpeak r 16 u 0 read voltage peak level with reset C see peak detection 0x1b gain r/w 8 u 0 set pga gain of analog inputs C see table 33 0x1c ibgain r/w 12 s 0 set matchi ng gain for ib current input 0x1d wgain r/w 12 s 0 set watt gain register 0x1e vargain r/w 12 s 0 set var gain register 0x1f vagain r/w 12 s 0 set va gain register 0x20 wattos r/w 16 s 0 set watt offset register 0x21 varos r/w 16 s 0 set var offset register 0x22 irmsos r/w 12 s 0 set current rms offset register 0x23 vrmsos r/w 12 s 0 set voltage rms offset register 0x24 wdiv r/w 8 u 0 set watt energy scaling register 0x25 vardiv r/w 8 u 0 set va r energy scaling register 0x26 vadiv r/w 8 u 0 set va energy scaling register 0x27 cf1num r/w 16 u 0 set cf1 numerator register 0x28 cf1den r/w 16 u 0x003f set cf1 denominator register
preliminary technical data ade7169f16 rev. prd | page 37 of 140 address maddpt[6:0] name r/w length signed /unsigned default value description 0x29 cf2num r/w 16 u 0 set cf2 numerator register 0x2a cf2den r/w 16 u 0x003f set cf2 denominator register 0x3d calmode r/w 8 u 0 set calibration mode energy measurement internal registers details table 28. mode1 register (0x0b) bit location bit mnemonic default value description 7 swrst 0 setting this bit will reset all of the energy measurement registers to their default values 6 diszxlpf 0 setting this bit disables the zero-crossing lowpass filter 5 inte 0 setting this bit enables the digita l integrator for use with a di/dt sensor 4 swapbits 0 setting this bit swaps ch1 & ch2 adcs 3 pwrdn 0 setting this bit powers down voltage and current adcs 2 discf2 1 setting this bit disables frequency output cf2 1 discf1 1 setting this bit disables frequency output cf1 0 dishpf 0 setting this bit disables the hpfs in voltage and current channels table 29. mode2 register (0x0c) bit location bit mnemonic default value description 7-6 cf2sel[1:0] 01 configuration bits for cf2 output cf2sel[1:0] source 00 cf2 frequency is proportional to active power 01 cf2 fr equency is proportional to reactive power 1x cf2 freq uency is proportional to apparent power or irms 5-4 cf1sel[1:0] 00 configuration bits for cf1 output cf1sel[1:0] source 00 cf1 frequency is proportional to active power 01 cf1 fr equency is proportional to reactive power 1x cf1 freq uency is proportional to apparent power or irms 3 varmscfcon 0 configuration bits for appare nt power or irms for cf1 and cf2 outputs 0 if cf1sel[1:0]=1x, cf1 is proportional to va if cf2sel[1:0]=1x, cf2 is proportional to va 1 if cf1sel[1:0]=1x, cf1 is proportional to irms if cf2sel[1:0]=1x, cf2 is proportional to irms note that cf1 cannot be proportional to va if cf2 is proportional to irms and vice versa 2 zxrms 0 logic one enables update of rm s values synchronously to voltage zx 1 freqsel 0 configuration bits to select per iod or frequency measurement for per_freq register (0ah) 0 per_freq register holds a period measurement 1 per_freq register holds a frequency measurement 0 reserved 1 this bit should be kept to one table 30. wavmode register (0x0d) bit location bit mnemonic default value description
ade7169f16 preliminary technical data rev. prd | page 38 of 140 7-5 wav2sel[2:0] 0 waveform 2 selection for samples mode wav2sel[2:0] source 000 current 001 voltage 010 active power multiplier output 011 reactive power multiplier output 100 va multiplier output 101 irms lpf output others reserved 4-2 wav1sel[2:] 0 waveform 1 selection for samples mode wav1sel[2:0] source 000 current 001 voltage 010 active power multiplier output 011 reactive power multiplier output 100 va multiplier output 101 irms lpf output (low 24-bit) others reserved 1-0 dtrt[1:0] 0 waveform sa mples output data rate dtrt[1:0] update rate (clock=mclk/5=819.2khz) 00 25.6ksps(clock/32) 01 12.8ksps(clock/64) 10 6.4ksps(clock/128) 11 3.2ksps(clock/256) table 31. nlmode register (0x0e) bit location bit mnemonic default value description 7 reserved 0 reserved 6 irmsnoload 0 logic one enables irms no-load thresold detection. the level is defined by the setting of the vanoloadbits. 5-4 vanoload[1:0] 0 apparent power no-load threshold [1:0] 00 no-load detection disabled 01 no-load enabled with threshold = 0.030% of full scale 10 no-load enabled with threshold = 0.015% of full scale 11 no-load enabled with threshold = 0.0075% of full scale 3-2 varnoload[1:0] 0 reacti ve power no-load threshold [1:0] 00 no-load detection disabled 01 no-load enabled with threshold = 0.015% of full scale 10 no-load enabled with threshold = 0.0075% of full scale 11 no-load enabled with threshold = 0.0037% of full scale 1-0 apnoload[1:0] 0 active power no-load threshold [1:0] 00 no-load detection disabled 01 no-load enabled with threshold = 0.015% of full scale 10 no-load enabled with threshold = 0.0075% of full scale 11 no-load enabled with threshold = 0.0037% of full scale table 32. accmode register (0x0f) bit bit default description
preliminary technical data ade7169f16 rev. prd | page 39 of 140 location mnemonic value 7 ichannel 0 this bit indicate the current channe l used to measure energy in anti- tampering mode. 0 C channel a 1 C channel b 6 faultsign 0 configuration bit to select event that will trigger a fault interrupt 0 C fault interrupt occurs when part enters fault mode 1 C fault interrupt occurs when part enters normal mode 5 varsign 0 configuration bit to select event that will trigger an reactive power sign interrupt 0 C varsign interrupt occurs when reactive power changes from positive to negative 1 - varsign interrupt occurs when reactive power changes from negative to positive 4 apsign 0 configuration bit to select event that will trigger an active power sign interrupt 0 C apsign interrupt occurs when ac tive power changes from positive to negative 1 - apsign interrupt occurs when ac tive power changes from negative to positive 3 absvarm 0 logic one enables absolute value accumulation of reactive power in energy register and pulse output 2 savarm 0 logic one enables reactive power accumulation depending on the sign of the active power: if active power is positive, va r is accumulated as it is; if active power is negative, the si gn of the var is reversed for the accumulation. this accumulation mode affects bot h the var registers and the varcf output. 1 poam 0 logic one enables positive only accumulation of active power in energy register and pulse output 0 absam 0 logic one enables absolute value accumulation of active power in energy register and pulse output table 33. gain register (0x1b) bit location bit mnemonic default value description 7 - 5 pga2[2:0] 0 these bits define the voltage channel input gain [2:0] 000 gain = 1 001 gain = 2 010 gain = 4 011 gain = 8 100 gain = 16 4 - 3 reserved 0 reserved 2 - 0 pga1[2:0] 0 these bits define the current channel input gain [2:0] 000 gain = 1 001 gain = 2 010 gain = 4 011 gain = 8 100 gain = 16 table 34. calmode register (0x3d) bit bit default description
ade7169f16 preliminary technical data rev. prd | page 40 of 140 location mnemonic value 7 C 6 reserved 0 these bits should be kept cleared for proper operation 5 - 4 sel_i_ch[1:0] 0 these bits define the cu rrent channel used for energy measurements [1:0] 00 current channel automatically sele cted by the tampering condition 01 current channel connected to i a 10 current channel connected to i b 11 current channel automatically selected by the tampering condition 3 v_ch_short 0 logic one short voltage channel to ground 2 i_ch_short 0 logic one short current channels to ground 1 - 0 reserved table 35. interrupt status register 1 sfr (mirqstl, 0xdc) bit location interrupt flag description 7 adeirqflag this bit is set if any of the ade status flags that are enabled to generate an ade interrupt are set. this bit is automati cally cleared when all of the enabled ade status flags are cleared. 6 reserved reserved. 5 faultsign logic one indicates that the fault mode has changed according to the configuration of the accmode register 4 varsign logic one indicates that the reactive power si gn changed according to the configuration of accmode register 3 apsign logic one indicates that the active power sign changed according to the configuration of accmode register 2 vanoload logic one indicates that an interrupt was ca used by apparent power no-load detected. this interrupt is also used to reflect the part enteri ng the irms no load mode. 1 rnoload logic one indicates that an interrupt was caused by reactive power no-load detected. 0 apnoload logic one indicates that an interrupt was caused by active power no-load detected. table 36. interrupt status register 2 sfr (mirqstm, 0xdd) bit location interrupt flag description 7 cf2 logic one indicates that a pulse on cf2 has been issued. the flag is set even if cf2 pulse output is not enabled by clearing bit 2 of mode1 register. 6 cf1 logic one indicates that a pulse on cf1 has been issued. the flag is set even if cf1 pulse output is not enabled by clearing bit 1 of mode1 register. 5 vaeof logic one indicates that th e vahr register has overflowded 4 reof logic one indicates that the varhr register has overflowded 3 aeof logic one indicates that th e watthr register has overflowded 2 vaehf logic one indicates that the vahr register is half full 1 rehf logic one indicates that the varhr register is half full 0 aehf logic one indicates that the watthr register is half full table 37. interrupt status register 3 sfr (mirqsth, 0xde) bit location interrupt flag description 7 reset indicates the end of a reset (for both sofware or hardware reset). 6 - reserved 5 wfsm logic one indicates that new data is present in the waveform registers 4 pki logic one indicates that current channel has exceeded the ipklvl value 3 pkv logic one indicates that voltage ch annel has exceeded the vpklvl value.
preliminary technical data ade7169f16 rev. prd | page 41 of 140 2 cycend logic one indicates the end of the energy accu mulation over an integer number of half line cycles. 1 zxto logic one indicates that no zero crossing on the line voltage happened for the last zxtout half line cycles. 0 zx logic one indicates detection of a zero crossing in the voltage channel. table 38. interrupt enable register 1 sfr (mirqenl, 0xd9) bit location interrupt flag description 7-6 reserved reserved. 5 faultsign when this bit is set, the faultsign bit se t creates a pending ade interrupt to the 8052 core. 4 varsign when this bit is set, the varsign bit set creates a pending ade interrupt to the 8052 core. 3 apsign when this bit is set, the apsign bit set creates a pending ade interrupt to the 8052 core. 2 vanoload when this bit is set, the vanoload bit se t creates a pending ade interrupt to the 8052 core. 1 rnoload when this bit is set, the rnoload bit se t creates a pending ade interrupt to the 8052 core. 0 apnoload when this bit is set, the apnoload bit se t creates a pending ade interrupt to the 8052 core. table 39. interrupt enable register 2 sfr (mirqenm, 0xda) bit location interrupt flag description 7 cf2 when this bit is set, a cf2 pulse issued creates a pending ade interrupt to the 8052 core. 6 cf1 when this bit is set, a cf1 pulse issued creates a pending ade interrupt to the 8052 core. 5 vaeof when this bit is set, the vaeof flag se t creates a pending ade interrupt to the 8052 core. 4 reof when this bit is set, the reof flag se t creates a pending ade interrupt to the 8052 core. 3 aeof when this bit is set, the aeof flag set creates a pending ade interrupt to the 8052 core. 2 vaehf when this bit is set, the vaehf flag se t creates a pending ade interrupt to the 8052 core. 1 rehf when this bit is set, the rehf flag se t creates a pending ade interrupt to the 8052 core. 0 aehf when this bit is set, the aehf flag set creates a pending ade interrupt to the 8052 core. table 40. interrupt enable register 3 sfr (mirqenh, 0xdb) bit location interrupt flag description 7-6 - reserved 5 wfsm when this bit is set, the wfsm flag se t creates a pending ade interrupt to the 8052 core. 4 pki when this bit is set, th e pki flag set creates a pending ade interrupt to the 8052 core. 3 pkv when this bit is set, th e pkv flag set creates a pending ade interrupt to the 8052 core.. 2 cycend when this bit is set, the cycend flag set creates a pending ade interrupt to the 8052 core. 1 zxto when this bit is set, th e zxto flag set creates a pendin g ade interrupt to the 8052 core. 0 zx when this bit is set, the zx flag set creates a pending ade interrupt to the 8052 core. analog inputs the ade7169f16 has two fully differential voltage input channels. the maximum differential input voltage for input pairs vp/vn and ip/in are 0.5 v. in addition, the maximum signal level on analog inputs for vp/vn and ip/ in is 0.5 v with respect to agnd. each analog input channel has a pga (programmable gain amplifier) with possible gain selections of 1, 2, 4, 8, and 16. the gain selections are made by writing to the gain register in the energy measurement register listsee table 33 and figure 17. bits 0 to 2 select the gain for the pga in the current channel, and the gain selection for the pga in voltage channel is made via bits 5 to 7. figure 16 shows how a gain selection for the current channel is made using the gain register.
ade7169f16 preliminary technical data rev. prd | page 42 of 140 v1p v1n v in k ? v in gain[7:0] 76 5 4 3 2 1 0 00 0 0 0 0 0 0 gain (k) selection figure 16. pga in current channel in addition to the pga, channel 1 also has a full-scale input range selection for the adc. the adc analog input range selection is also made using the gain registersee figure 17. as mentioned previously, the maximum differential input voltage is 0.5 v. reserved gain register* current and voltage channels pga control 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 addr: 1bh * register contents show power-on defaults pga 2 gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 pga 1 gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 figure 17. ade7169f16 analog gain register analog to digital conversion the ade7169f16 has two sigma-delta analog to digital converters (adc). the outputs of these adcs are mapped directly to waveform sampling sfrs (address 0xe2 to 0xe7) and are used for the energy measurement internal digital signal processing. in psm1 (battery mode)and psm2 (sleep mode), the adcs are powered down to minimize power consumption. for simplicity, the block diagram in figure 18 shows a first- order - adc. the converter is made up of the - modulator and the digital low-pass filter. 24 digital low-pass filter r c analog low-pass filter + ? v ref 1-bit dac integrator mclk/5 latched comparator .....10100101..... + ? figure 18. first-order -? adc a - ? modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ade7169f16, the sampling clock is equal to mclk/5. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and therefore the bit stream) can approach that of the input signal level. for any given input value in a single sampling interval, the data from the 1-bit adc is virtually meaningless. only when a large number of samples are averaged is a meaningful result obtained. this averaging is carried out in the second part of the adc, the digital low-pass filter. by averaging a large number of bits from the modulator, the low- pass filter can produce 24-bit data-words that are proportional to the input signal level. the - converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. the first is oversampling. oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. for example, the sampling rate in the ade7169f16 is mclk/5 (819.2 khz) and the band of interest is 40 hz to 2 khz. oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered see figure 19. however, oversampling alone is not efficient enough to improve the signal-to-noise ratio (snr) in the band of interest. for example, an oversampling ratio of 4 is required just to increase the snr by only 6 db (1 bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. in the - modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. the result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. this noise shaping is shown in figure 19. 409.6 0 819.2 2 noise s ignal digital filter a ntilalia s filter (rc) sampling frequency high resolution output from digital lpf shaped noise 409.6 0 819.2 2 noise s ignal frequency (khz) frequency (khz) 02875-0-047 figure 19. noise reduction due to oversampling and noise shaping in the analog modulator
preliminary technical data ade7169f16 rev. prd | page 43 of 140 anti-aliasing filter figure 18 also shows an analog low-pass filter (rc) on the input to the modulator. this filter is present to prevent aliasing. aliasing is an artifact of all sampled systems. aliasing means that frequency components in the input signal to the adc, which are higher than half the sampling rate of the adc, appear in the sampled signal at a frequency below half the sampling rate. figure 20 illustrates the effect. frequency components (arrows shown in black) above half the sampling frequency (also know as the nyquist frequency, i.e., 409.6 khz) are imaged or folded back down below 409.6 khz. this happens with all adcs regardless of the architecture. in the example shown, only frequencies near the sampling frequency, i.e., 819.2 khz, move into the band of interest for metering, i.e., 40 hz to 2 khz. this allows the use of a very simple lpf (low-pass filter) to attenuate high frequency (near 819.2 khz) noise, and prevents distortion in the band of interest. for conventional current sensors, a simple rc filter (single-pole lpf) with a corner frequency of 10 khz produces an attenuation of approximately 40 db at 819.2 khz see figure 20. the 20 db per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. however, for a di/dt sensor such as a rogowski coil, the sensor has a 20 db per decade gain. this neutralizes the C20 db per decade attenuation produced by one simple lpf. therefore, when using a di/dt sensor, care should be taken to offset the 20 db per decade gain. one simple approach is to cascade two rc filters to produce the C40 db per decade attenuation needed. sampling frequency image frequencies a liasing effect s 0 2 409.6 819.2 frequency (khz) figure 20. adc and signal processing in current channel outline dimensions adc transfer function both adcs in the ade7169f16 are designed to produce the same output code for the same input signal level. with a full- scale signal on the input of 0.5 v and an internal reference of 1.2 v, the adc output code is nominally 2,684,354 or 28f5c2h. the maximum code from the adc is 4,194,304; this is equivalent to an input signal level of 0.794 v. however, for specified performance, it is recommended that the full-scale input signal level of 0.5 v not be exceeded. current channel adc figure 21 shows the adc and signal processing chain for the current channel. in waveform sampling mode, the adc outputs a signed twos complement 24-bit data-word at a maximum of 25.6 ksps (mclk/160). with the specified full-scale analog input signal of 0.5 v (or 0.25 v or 0.125 vsee the analog inputs section) the adc produces an output code that is approximately between 0x28f5c2 (+2,684,354d) and 0xd70a3e (C2,684,354d)see figure 21. x1, x2, x4, x8, x16 analog input range digital integrator* dt hpf adc reference v1 0v 0.5v, 0.25v, 0.125v, 62.5mv, 31.3mv current channel waveform data range active and reactive power calculation waveform sample register current rms (irms) calculation 50hz iap in pga1 i {gain[2:0]} *when digital integrator is enabled, full-scale output data is attenuated depending on the signal frequency because the integrator has a ?20db/decade frequency response. when disabled, the output will not be further attenuated. 0x d70a3e 0x 000000 0x 28f5c2 current channel waveform data range after integrator (50hz) 0xcbd330 0x 000000 0x 342cd0 60hz current channel waveform data range after integrator (60hz) 0xd487b0 0x 000000 0x 2b7850 mode1[5] hpf adc pga1 ibp figure 21. adc and signal processing in current channel
ade7169f16 preliminary technical data rev. prd | page 44 of 140 voltage channel adc figure 21 shows the adc and signal processing chain for the voltage channel. in waveform sampling mode, the adc outputs a signed twos complement 24-bit data-word at a maximum of 25.6 ksps (mclk/160). the adc produces an output code that is approximately between 0x28f5 (+10,485d) and 0xd70b (C10,485d)see figure 22. x1, x2, x4, x8, x16 analog input range hpf adc reference v2 0v 0.5v, 0.25v, 0.125v, 62.5mv, 31.3mv waveform sample register voltage rms (vrms) calculation vp pga2 v2 {gain[7:5]} voltage channel waveform data range 0xd70b 0x 0000 0x28f5 a ctive and reactiv e power calculation lpf1 f ? 3db = 63.7hz mode1[6] zx signal data range for 60hz signal 0xe230 0x 0000 0x1dd0 zx detection zx signal data range for 50hz signal 0xdfc9 0x 0000 0x2037 voltage peak detect figure 22. adc and signal processing in voltage channel channel sampling the waveform samples of the current adc and voltage adc can also be routed to the waveform registers to be read by the mcu core. the active, reactive, apparent power, and energy calculation remain uninterrupted during waveform sampling. when in waveform sampling mode, one of four output sample rates can be chosen by using bits 0 and 1 of the wavmode register (wavsel1,0). the output sample rate can be 25.6 ksps, 12.8ksps, 6.4 ksps, or 3.2 kspssee table 30. if the wfsm enable bit is set in the interrupt enable register 3 sfr (mirqenh, 0xdb), the 8052 core has a pending ade interrupt. the sampled signals selected in the wavmode register will be latched into the waveform sfrs when the waveform high byte (wav1h or wav2h) is read. the ade interrupt stays active until the wfsm status bit is clearedsee energy measurement interrupts section. fault detection the ade7169f16 incorporates a fault detection scheme that warns of fault conditions and allows the ade7169f16 to continue accurate measurement during a fault event. the ade7169f16 does this by continuously monitoring both current inputs (ia and ib). these currents will be referred for ease of understanding as phase and neutral (return) currents. in the ade7169f16, a fault condition is defined when the difference between i a and i b is greater than 6.25% of the active channel. if a fault condition is detected and the inactive channel is larger than the active channel, the ade7169f16 automatically switches to current measurement to the inactive channel. during a fault, the active, reactive, current rms and apparent powers are generated using the larger of the two currents. on power-up, i a is the current input selected for active, reactive, and apparent power and irms calculations. to prevent false alarm, averaging is done for the fault detection and a fault condition is detected approximately 1 second after the event. the fault detection is automatically disabled when the voltage signal is less than 0.3% of the full-scale input range. this eliminates false detection of a fault due to noise at light loads. because the ade7169f16 looks for a difference between the voltage signals on i a and i b , it is important that both current transducers be closely matched. channel selection indication the current channel selected for measurement is indicated by bit 7 (ichannel) in the accmode register (0x0f). when this bit is cleared, i a is selected and when it is set, i b is selected.
preliminary technical data ade7169f16 rev. prd | page 45 of 140 the ade7169f16 automatically switches from one channel to the other and reports the channel configuration in the accmode register (0x0f). the current channel selected for measurement can also be forced. setting one of the selch1a and selch1b bits in the calmode register (0x3d) selects i a and i b respectively. when both bits are cleared or set, the current channel used for measurement is selected automatically based on the fault detection. fault indication the ade7169f16 provides an indication of the part going in or out of a fault condition. the new fault condition is indicated by the faultsign flag (bit5) in the interrupt status register 1 sfr (mirqstl, 0xdc). when faultsign bit (bit 6) of accmode register (0x0f) is cleared, the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when the part is entering fault condition. when faultsign bit (bit 6) of accmode register (0x0f) is set, the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when the part is entering normal condition. when the faultsign bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), and the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set, the 8052 core has a pending ade interrupt. fault with active input greater than inactive input if i a is the active current input (that is, being used for billing), and the voltage signal on i b (inactive input) falls below 93.75% of i a , and the faultsign bit (bit 6) of accmode register (0x0f) is cleared, the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set. both analog inputs are filtered and averaged to prevent false triggering of this logic output. as a consequence of the filtering, there is a time delay of approximately 3 s on the logic output after the fault event. the faultsign flag is independent of any activity. because i a is the active input and it is still greater than i b , billing is maintained on i a , that is, no swap to the i b input occurs. i a remains the active input. fault with inactive input greater than active input if the difference between i b , the inactive input, and i a , the active input (that is, being used for billing), becomes greater than 6.25% of i b , and the faultsign bit (bit 6) of accmode register (0x0f) is cleared, the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set. the analog input i b becomes the active input. again, a time constant of about 3 s is associated with this swap. i a does not swap back to the active channel until i a is greater than i b and the difference between i a and i b in this orderbecomes greater than 6.25% of i b . however, if faultsign bit (bit 6) of accmode register (0x0f) is set, the faultsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set as soon as i a is within 6.25% of i b . this threshold eliminates potential chatter between i a and i b . calibration concerns typically, when a meter is being calibrated, the voltage and current circuits are separated as shown in figure 23. this means that current passes through only the phase or neutral circuit. figure 23 shows current being passed through the phase circuit. this is the preferred option, because the ade7169f16 starts billing on the input i a on power-up. the phase circuit ct is connected to i a in the diagram. as the current sensors are not perfectly matched, it is important to match current inputs. the ade7169f16 provides a gain calibration register for i b, ibgain (address 0x1c). ibgain is a 12-bit signed 2-complement register that provides a gain resolution of 0.0244%/lsb. for calibration, a first measurement should be done on i a by setting sel_i_ch bits to 0b01 in the calmode register (0x3d). this measurement should be compared to the measurement on i b . measuring i b can be forced by setting sel_i_ch bits to 0b10 in the calmode register (0x3d). the gain error between these two measurements can be evaluated using: () () ( ) () a a b i t measuremen i t measuremen i t measuremen error ? = % the two channels i a and i b can then be matched by writing: C error(%) / (1 + error (%)) * 2 12 to ibgain register. this matching adjustment will be valid for all energy measurements, active power, reactive power, irms, and apparent power, made by the ade7169f16. agnd i b i n i a r f r f c f c f ct ct rb rb 0v v a 0 ib phase neutral rf ra v p r f v n c t c f v test current 240v rms figure 23. fault conditions for inactive input greater than active input di/dt current sensor and digital integrator a di/dt sensor detects changes in magnetic field caused by ac
ade7169f16 preliminary technical data rev. prd | page 46 of 140 current. figure 24 shows the principle of a di/dt current sensor. magnetic field created by current (directly proportional to current) + emf (electromotive force) ? induced by changes in magnetic flux density (di/dt) 02875-0-035 figure 24. principle of a di/dt current sensor the flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. the changes in the magnetic flux density passing through a conductor loop generate an electromotive force (emf) between the two ends of the loop. the emf is a voltage signal, which is proportional to the di/dt of the current. the voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. the current signal needs to be recovered from the di/dt signal before it can be used. an integrator is therefore necessary to restore the signal to its original form. the ade7169f16 has a built-in digital integrator to recover the current signal from the di/dt sensor. the digital integrator on the current channel is switched off by default when the ade7169f16 is powered up. setting inte bit in the mode1 register (0x0b) turns on the integrator. figure 25 to figure 28 show the magnitude and phase response of the digital integrator. frequency (hz) 10 gain (db) 0 ?10 ?20 ?30 ?40 ?50 10 2 10 3 02875-0-036 figure 25. combined gain response of the digital integrator and phase compensator frequency (hz) 10 2 10 3 02875-0-037 freq ?88.0 phase (degrees) ?88.5 ?89.0 ?89.5 ?90.0 ?90.5 figure 26. combined phase response of the digital integrator and phase compensator frequency (hz) ?1.0 ?6.0 40 70 45 gain (db) 50 55 60 65 ?1.5 ?2.0 ?2.5 ?3.5 ?4.5 ?5.5 ?3.0 ?4.0 ?5.0 02875-0-038 figure 27. combined gain response of the digital integrator and phase compensator (40 hz to 70 hz) ?89.75 ?89.80 ?89.85 ?89.90 ?89.95 ?90.00 frequency (hz) phase (degrees) 40 45 70 50 55 60 65 ?90.05 ?89.70 02875-0-039 figure 28. combined phase response of the digital integrator and phase compensator (40 hz to 70 hz) note that the integrator has a C20 db/dec attenuation and an approximately C90 phase shift. when combined with a di/dt
preliminary technical data ade7169f16 rev. prd | page 47 of 140 sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. the di/dt sensor has a 20 db/dec gain associated with it. it also generates signifi- cant high frequency noise, therefore a more effective anti- aliasing filter is needed to avoid noise due to aliasingsee the anti-aliasing filter section. when the digital integrator is switched off, the ade7169f16 can be used directly with a conventional current sensor such as a current transformer (ct) or with a low resistance current shunt. power quality measurements zero-crossing detection the ade7169f16 has a zero-crossing detection circuit on the voltage channel. this zero crossing is used to produce an external zero-crossing signal (zx), and it is also used in the calibration mode. the zero-crossing is generated, by default, from the output of lpf1. as explained in the following paragraph, this filter has a low cut-off frequency and is intended for use for 50 and 60hz system. if needed this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection. if the voltage input fundamental frequency is below 60hz and a time delay in zx detection is acceptable, it is recommended to enable lpf1. enabling lpf1 will limit the variability in the zx detection by eliminating the high frequency components. figure 29 shows how the zero-crossing signal is generated. x1, x2, x4, x8, x16 adc 2 reference lpf1 f ? 3db = 63.7hz pga2 {gain [7:5]} vp vn v 2 zero cross zx hpf mode1[6] 43.24 @ 60hz 1.0 0.73 zx v2 lpf1 figure 29. zero-crossing detection on voltage channel the zero-crossing signal zx is generated from the output of lpf1 (bypassed or not). lpf1 has a single pole at 63.7 hz (at mclk = 4.096 mhz). as a result, there is a phase lag between the analog input signal v2 and the output of lpf1. the phase lag response of lpf1 results in a time delay of approximately 2 ms (@ 60 hz) between the zero crossing on the analog inputs of the voltage channel and zx detection. the zero-crossing detection also drives the zx flag in the interrupt status register 3 sfr (mirqsth, 0xde). if the zx bit in the interrupt enable register 3 sfr (mirqenh, 0xdb) is set, the 8052 core has a pending ade interrupt. the ade interrupt stays active until the zx status bit is clearedsee energy measurement interrupts section. zero-crossing timeout the zero-crossing detection also has an associated timeout register, zxtout. this unsigned, 12-bit register is decremented (1 lsb) every 160/mclk seconds. the register is reset to its user programmed full-scale value every time a zero crossing is detected on the voltage channel. the default power on value in this register is 0xfff. if the internal register decrements to 0 before a zero crossing is detected and the zxtout flag in the interrupt status register 3 sfr (mirqsth, 0xde) is set. if the zxto bit in the interrupt enable register 3 sfr (mirqenh, 0xdb) is set, the 8052 core has a pending ade interrupt. the ade interrupt stays active until the zxto status bit is clearedsee energy measurement interrupts section. the zxout register (address 0x11) can be written or read by the usersee energy measurement register list. the resolution of the register is 160/mclk seconds per lsb. thus the maxi- mum delay for an interrupt is 0.16 second (128/mclk 2 12 ) when mclk = 4.096mhz. figure 30 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than clkin/160 zxtout seconds. 12-bit internal register value zxtout voltage channel zxto flag bit figure 30. zero-crossing timeout detection period or frequency measurements the ade7169f16 provides the period or frequency measurement of the line. the period or frequency measurement is selected by clearing or setting freqsel bit in the mode2 register (0x0c). the period/frequency register is an unsigned 16-bit register and is updated every period. if lpf1 is enabled, a settling time of 1.8 seconds is associated with this filter before the measurement is stable.
ade7169f16 preliminary technical data rev. prd | page 48 of 140 when the period measurement is selected, the measurement has a 2.44 s/lsb (mclk/10) when mclk = 4.096 mhz, which represents 0.014% when the line frequency is 60 hz. when the line frequency is 60 hz, the value of the period register is approximately 0d6827. the length of the register enables the measurement of line frequencies as low as 12.5 hz. the period register is stable at 1 lsb when the line is established and the measurement does not change. when the frequency measurement is selected, the measurement has a 0.0625 hz/lsb resolution when mclk = 4.096mhz which represents 0.104% when the line frequency is 60hz. when the line frequency is 60hz, the value of the frequency register is 0d960. the frequency register is stable at 4 lsb when the line is established and the measurement does not change. line voltage sag detection in addition to the detection of the loss of the line voltage signal (zero crossing), the ade7169f16 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. this condition is illustrated in figure 31. sagcyc [7:0] = 0x04 3 line cycles sag reset low when voltage channel exceeds saglvl [15:0] and sag flag reset full scale saglvl [15:0] sag flag voltage channel figure 31. ade7169f16 sag detection figure 31 shows the line voltage falling below a threshold that is set in the sag level register (saglvl[15:0]) for three line cycles. the quantities 0 and 1 are not valid for the sagcyc register, and the contents represent one more than the desired number of full line cycles. for example, when the sag cycle (sagcyc[7:0]) contains 0x04, the sag flag in the power management interrupt flag sfr (ipsmf, 0xf8) is set at the end of the third line cycle for which the line voltage falls below the threshold. if the sag enable bit in the power management interrupt enable sfr (ipsme, 0xec) is set the 8052 core has a pending power supply monitoring interrupt. the psm interrupt stays active until the sag status bit is clearedsee power supply monitor interrupt (psm) section. on figure 31, the sag flag is set as soon as the fifth line cycle from the time when the signal on the voltage channel first dropped below the threshold level. sag level set the contents of the sag level register (2 bytes) are compared to the absolute value of the output from lpf1. therefore, when lpf1 is enabled, writing 0x2038 to the sag level register puts the sag detection level at full scale C see figure 22. writing 0x00 or 0x01 puts the sag detection level at 0. the sag level register is compared to the input of the zx detection and detection is made when the contents of the sag level register are greater. peak detection the ade7169f16 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. figure 32 illustrates the behavior of the peak detection for the voltage channel. both voltage and current channels are monitored at the same time. pkv reset low when rststatus register is read vpklvl[15:0] v 2 read rststatus register pkv interrupt flag figure 32. ade7169f16 peak level detection figure 32 shows a line voltage exceeding a threshold that is set in the voltage peak register (vpklvl[15:0]). the voltage peak event is recorded by setting the pkv flag in the interrupt status register 3 sfr (mirqsth, 0xde). if the pkv enable bit is set in the interrupt enable register 3 sfr (mirqenh, 0xdb), the 8052 core has a pending ade interrupt. similarly, the current peak event is recorded by setting the pki flag in interrupt status register 3 sfr (mirqsth, 0xde). the ade interrupt stays active until the pkv or pki status bits are clearedsee energy measurement interrupts section. peak level set the contents of the vpklvl and ipklvl registers are respectively compared to the absolute value of the voltage and current channels two most significant bytes. thus, for example, the nominal maximum code from the current channel adc with a full-scale signal is 0x28f5c2see the current channel adc section. therefore, writing 0x28f5 to the ipklvl register, for example, puts the current channel peak detection level at full scale and sets the current peak detection to its least sensitive value. writing 0x00 puts the current channel detection level at 0. the detection is done by comparing the contents of the ipklvl register to the incoming current channel sample. the pki flag indicates that the peak level is exceeded if the pki or
preliminary technical data ade7169f16 rev. prd | page 49 of 140 pkv bits are set in interrupt enable register 3 sfr (mirqenh, 0xdb), the 8052 core has a pending ade interrupt. peak level record the ade7169f16 records the maximum absolute value reached by the voltage and current channels in two different registers ipeak and vpeak, respectively. vpeak and ipeak are 16-bit unsigned registers. these registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the vpeak or ipeak register. the contents of the vpeak register correspond to the maximum absolute value observed on the voltage channel input. the contents of ipeak and vpeak represent the maximum absolute value observed on the current and voltage input respectively. reading the rstvpeak and rstipeak registers clears their respective contents after the read operation. phase compensation the ade7169f16 must work with transducers, which could have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not uncommon for a current transformer (ct). these phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the ade7169f16 provides a means of digitally calibrating these small phase errors. the ade7169f16 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1 to 0.5. correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. the phase calibration register (phcal[7:0]) is a twos comple- ment signed single-byte register that has values ranging from 0x82 (C126d) to 0x68 (104d). the register is centered at 0x40, so that writing 0x40 to the register gives 0 delay. by changing the phcal register, the time delay in the voltage channel signal path can change from C 231.93 s to +48.83 s (mclk = 4.096 mhz). one lsb is equivalent to 1.22 s (mclk/5) time delay or advance. a line frequency of 60 hz gives a phase resolution of 0.026 at the fundamental (i.e., 360 1.22 s 60 hz) or 0.00732% of the line period. similarly, a line frequency of 50hz gives a phase resolution of 0.022 at the fundamental or 0.0061% of the line period. figure 33 illustrates how the phase compensation is used to remove a 0.1 phase lead in current channel due to the external transducer. to cancel the lead (0.1) in current channel, a phase lead must also be introduced into voltage channel. the resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.026. the phase lead is achieved by introducing a time advance into voltage channel. a time advance of 4.88 s is made by writing ?4 (0x3c) to the time delay block, thus reducing the amount of time delay by 4.88 s, or equivalently, a phase lead of approximately 0.1 at line frequency of 60 hz. 0x3c represents C4 because the register is centered with 0 at 0x40. 1 1 0 1 0 0 1 70 pga1 ip a in i adc 1 hpf 24 pga2 vp v v adc 2 delay block 1.22 s/lsb 24 lpf2 v i 60hz 0.1 i v channel 2 delay reduced by 4.48 s (0.1lead at 60hz) 0bh in phcal [5.0] phcal [7:0] --231.93 s to +48.83 s 60hz 1 1 figure 33. phase calibration ade7169f16 rms calculation root mean square (rms) value of a continuous signal v(t) is defined as vrms = = t rms dt t v t v 0 2 ) ( 1 (2) for time sampling signals, rms calculation involves squaring the signal, taking the average and obtaining the square root. the ade7169f16 implements this method by serially squaring the input, averaging them and then taking the root square of the average. the averaging part of this signal processing is done by implementing a low pass filter (lpf3 in figure 35 and figure 36). this lpf has a -3db cut-off frequency of 2hz when mclk = 4.096mhz. v ( t ) = ) sin( 2 t v where: v is the rms voltage. ( ) t v v t v 2 cos ) ( 2 2 2 ? = when this signal goes through lpf3, the cos(2 t) term is attenuated and only the dc term v rms 2 goes through C see figure 34. v lpf3 input v(t)= ( ) t v v t v 2 cos ) ( 2 2 2 ? = v t v ) ( 2 2 = ) sin( 2 t v ? ? figure 34. ade7169f16 rms signal processing
ade7169f16 preliminary technical data rev. prd | page 50 of 140 the rms signals can be read from the waveform register by setting the wavmode register (0x0d) and setting the wfsm bit in the interrupt enable register 3 sfr (mirqenh, 0xdb). like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps. important: when the current input is larger than 40% of full scale, the irms waveform sample register does not represent the true rms value processed. the rms value processed with this level of input is larger than the 24 bit read by the waveform register making the value read truncated on the high end. current channel rms calculation the ade7169f16 simultaneously calculates the rms values for the current and voltage channel in different registers. the current channel rms calculation is done on the channel selected by sel_i_ch bits in the calmode register (0x3d). figure 35 shows the detail of the signal processing chain for the rms calculation on the current channel. the current channel rms value is processed from the samples used in the current channel waveform sampling mode. the current channel rms value is stored in an unsigned 24-bit register (irms). one lsb of the current channel rms register is equivalent to one lsb of a current channel waveform sample. the update rate of the current channel rms measurement is mclk/5. to minimize noise in the reading of the register, the irms register can also be configured to be updated only with the zero crossing of the voltage input. this configuration is done by setting zxrms bit in the mode2 register (0x0c). with the specified full-scale analog input signal of 0.5 v, the adc produces an output code that is approximately 0d2,684,354see the current channel adc section. the equivalent rms value of a full-scale ac signal is 0d1,898,124 (0x1cf68c). the current rms measurement provided in the ade7169f16 is accurate to within 0.5% for signal input between full scale and full scale/1000. the conversion from the register value to amps must be done externally in the microprocessor using an amps/lsb constant. i rms (t) lpf3 hpf1 0x00 + irmsos[11:0] irms[23:0] 2 26 2 25 sgn 2 27 2 17 2 16 2 18 24 24 digital integrator* dt hpf mode1[5] hpf current channel waveform data range with integrator off 0x d70a3e 0x 000000 0x 28f5c2 60hz current channel waveform data range with integrator on (60hz) 0xd487b0 0x 000000 0x 2b7850 ia ib figure 35. current channel rms signal processing current channel rms offset compensation the ade7169f16 incorporates a current channel rms offset compensation register (irmsos). this is a 12-bit signed register that can be used to remove offset in the current channel rms calculation. an offset could exist in the rms calculation due to input noises that are integrated in the dc component of v 2 (t). the offset calibration allows the content of the irms register to be maintained at 0 when no input is present on current channel. one lsb of the current channel rms offset is equivalent to 16,384 lsb of the square of the current channel rms register. assuming that the maximum value from the current channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 lsb of the current channel rms offset represents 0.23% of measurement error at C60 db down of full scale.
preliminary technical data ade7169f16 rev. prd | page 51 of 140 irms = 32768 2 0 + irmsos irms (4) where irms 0 is the rms measurement without offset correction. voltage channel rms calculation figure 36 shows the details of the signal processing chain for the rms calculation on voltage channel. the voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode. voltage channel rms value is stored in the unsigned 24-bit vrms register. the update rate of the voltage channel rms measurement is mclk/5. to minimize noise in the reading of the register, the vrms register can also be configured to be updated only with the zero crossing of the voltage input. this configuration is done by setting zxrms bit in the mode2 register (0x0c). with the specified full-scale ac analog input signal of 0.5 v, the output from the lpf1 swings between 0x28f5 and 0xd70b at 60 hzsee the voltage channel adc section. the equivalent rms value of this full-scale ac signal is approximately 0d1,898,124 (0x1cf68c) in the vrms register. the voltage rms measurement provided in the ade7169f16 is accurate to within 0.5% for signal input between full scale and full scale/20. the conversion from the register value to volts must be done externally in the microprocessor using a volts/lsb constant. voltage channel rms offset compensation the ade7169f16 incorporates a voltage channel rms offset compensation register (vrmsos). this is a 12-bit signed register that can be used to remove offset in the voltage channel rms calculation. an offset could exist in the rms calculation due to input noises and dc offset in the input samples. the offset calibration allows the contents of the vrms register to be maintained at 0 when no voltage is applied. one lsb of the voltage channel rms offset is equivalent to 64 lsb of the rms register. assuming that the maximum value from the voltage channel rms calculation is 0d1,898,124 with full-scale ac inputs, then one lsb of the voltage channel rms offset represents 3.37% of measurement error at C60 db down of full scale. vrms = vrms 0 + 64 x vrmsos (6) where vrms 0 is the rms measurement without offset correction. vrms[23:0] lpf3 lpf1 v oltage channel 0x28f5c2 0x00 + + vrmos[11:0] v olt a ge sign a l (v(t)) 2 16 sgn 2 15 2 8 2 7 2 6 0x 28f5 0x 0 0x d70b figure 36. voltage channel rms signal processing active power calculation active power is defined as the rate of energy flow from source to load. it is defined as the product of the voltage and current waveforms. the resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. the unit of power is the watt or joules/sec. equation 9 gives an expression for the instantaneous power signal in an ac system. v ( t ) = ) sin( 2 t v (7) i ( t ) = ) sin( 2 t i (8) where: v is the rms voltage. i is the rms current. ) ( ) ( ) ( t i t v t p = ) 2 cos( ) ( t vi vi t p ? = (9) the average power over an integral number of line cycles (n) is given by the expression in equation 10. p = = nt vi dt t p nt 0 ) ( 1 (10) where: t is the line cycle period. p is referred to as the active or real power. note that the active power is equal to the dc component of the instantaneous power signal p(t) in equation 9, i.e., vi. this is the relationship used to calculate active power in the ade7169f16. the instantaneous power signal p(t) is generated by multiplying the current and voltage signals. the dc component of the instantaneous power signal is then extracted by lpf2 (low-pass filter) to obtain the active power information. this process is illustrated in figure 37.
ade7169f16 preliminary technical data rev. prd | page 52 of 140 instantaneous power signal p(t) = v i-v i cos(2 t) active real power signal = v i 0x19999a vi 0xccccd 0x00000 current i(t) = 2 i sin( t) voltage v(t) = 2 v sin( t) 02875-0-060 figure 37. active power calculation since lpf2 does not have an ideal brick wall frequency responsesee figure 38, the active power signal has some ripple due to the instantaneous power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energysee the active energy calculation section. frequency (hz) ?24 1 db ?20 3 10 30 100 ?12 ?16 ?8 ?4 0 02875-0-061 figure 38. frequency response of lpf2 active power gain calibration figure 39 shows the signal processing chain for the active power calculation in the ade7169f16. as explained, the active power is calculated by low-pass filtering the instantaneous power signal. note that when reading the waveform samples from the output of lpf2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (wgain[11:0]). the gain is adjusted by writing a twos complement 12-bit word to the watt gain register. equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 12 2 1 wgain power active wgain output (11) for example, when 0x7ff is written to the watt gain register, the power output is scaled up by 50%. 0x7ff = 2047d, 2047/2 12 = 0.5. similarly, 0x800 = C2048d (signed twos complement) and power output is scaled by C50%. each lsb scales the power output by 0.0244%. the minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7ff to the watt gain register. this can be used to calibrate the active power (or energy) calculation in the ade7169f16. active power offset calibration the ade7169f16 also incorporates an active power offset register (wattos[15:0]). this is a signed twos complement 16-bit register that can be used to remove offsets in the active power calculationsee figure 37. an offset could exist in the power calculation due to crosstalk between channels on the pcb or in the ic itself. the offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. the 256 lsbs (wattos = 0x0100) written to the active power offset register are equivalent to 1 lsb in the waveform sample register. assuming the average value, output from lpf2 is 0xccccd (838,861d) when inputs on the voltage and current channels are both at full scale. at ?60 db down on the current channel (1/1000 of the current channel full-scale input), the average word value output from lpf2 is 838.861 (838,861/1,000). one lsb in the lpf2 output has a measurement error of 1/838.861 100% = 0.119% of the average value. the active power offset register has a resolution equal to 1/256 lsb of the waveform register, therefore the power offset correction resolution is 0.000464%/lsb (0.119%/256) at C60 db. active power sign detection the ade7169f16 detects a change of sign in the active power. the apsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) record when a change of sign according to bit apsign in the accmode register (0x0f) has occurred. if the apsign bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), the 8052 core has a pending ade interrupt. the ade interrupt stays active until the apsign status bit is clearedsee energy measurement interrupts section. when apsign in the accmode register (0x0f) is cleared (default), the apsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when a transition from positive to negative active power has occurred. when apsign in the accmode register (0x0f) is set, the apsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when a transition from negative to positive active power has occurred. active power no-load detection
preliminary technical data ade7169f16 rev. prd | page 53 of 140 the ade7169f16 includes a no-load threshold feature on the active energy that eliminates any creep effects in the meter. the ade7169f16 accomplishes this by not accumulating energy if the multiplier output is below the no-load threshold. when the active power is below the no-load threshold, the apnoload flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set. if the apnoload bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), the 8052 core has a pending ade interrupt. the ade interrupt stays active until the apnoload status bit is clearedsee energy measurement interrupts section. the no-load threshold level is selectable by setting bits apnoload in the nlmode register (0x0e). setting these bits to 0b00 disable the no-load detection and setting them to 0b01, 0b10 or 0b11 set the no-load detection threshold to 0.015%, 0.0075% and 0.0037% of the full-scale output frequency of the multiplier respectively. the iec62053-21 specification, states that the meter must start up with a load equal to or less than 0.4% ib. if the nominal voltage input and the maximum current represent 50% of the full scale adc input and imax = 400% of ib, the ade7169f16 no-load threshold options translate to 0.24% of ib, 0.12% of ib and 0.06% of ib respectively. wgain[11:0] wdiv[7:0] lpf2 current channel voltage channel output lpf2 time (nt) 5 clkin t active power signal + + watthr[23:0] outputs from the lpf2 are accumulated (integrated) in the internal active energy register upper 24 bits are accessible through watthr[23:0] register 23 0 48 0 waveform register values % wattos[15:0] 2 6 sgn 2 5 2 -6 2 -7 2 -8 + + for wavef0rm sampling to digital to frequency converter figure 39. ade7169f16 active energy calculation active energy calculation as stated earlier, power is defined as the rate of energy flow. this relationship can be expressed mathematically in equation 12. dt de p = (12) where: p is power. e is energy. conversely, energy is given as the integral of power. = pdt e (13) the ade7169f16 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal non-readable 49-bit energy register. the active energy register (watthr[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 14 expresses the relationship. 0 1 () ( ) t n e p t dt lim p nt t = ?? == ?? ? ? (14) where: n is the discrete time sample number. t is the sample period. the discrete time sample period ( t ) for the accumulation register in the ade7169f16 is 1.22s (5/mclk). as well as calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. figure 39 shows this discrete time integration or accumulation. the active power signal in the waveform register is continuously added to the internal active energy register.
ade7169f16 preliminary technical data rev. prd | page 54 of 140 the active energy accumulation depends on the setting of the poam and absam bits in the accmode register (0x0f). when both bits are cleared, the addition is signed and therefore negative energy is subtracted from the active energy contents. when both bits are set, the ade7169f16 is set to be in the more restrictive mode, the positive only accumulation mode. when poam bit in the accmode register (0x0f) is set, only positive power contributes to the active energy accumulation see the watt positive-only accumulation mode section. when absam bit in the accmode register (0x0f) is set, the absolute active power is used for the active energy accumulation see the watt absolute accumulation mode section. the output of the multiplier is divided by wdiv. if the value in the wdiv register is equal to 0, then the internal active energy register is divided by 1. wdiv is an 8-bit unsigned register. after dividing by wdiv, the active energy is accumulated in a 49-bit internal energy accumulation register. the upper 24 bits of this register are accessible through a read to the active energy register (watthr[23:0]). a read to the rwatthr register returns the content of the watthr register and the upper 24 bits of the internal register are cleared. as shown in figure 39, the active power signal is accumulated in an internal 49-bit signed register. the active power signal can be read from the waveform register by setting the wavmode register (0x0d) and setting the wfsm bit in the interrupt enable register 3 sfr (mirqenh, 0xdb). like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps. figure 40 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. the three curves displayed illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7ff, 0x000, and 0x800. the watt gain register is used to carry out power calibration in the ade7169f16. as shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7ff. 0x00,0000 0x7f,ffff 0x3f,ffff 0x40,0000 0x80,0000 w a tthr [23:0] 6.82 3.41 10.2 13.7 time (minutes) wgain = 0x7ff wgain = 0x000 wgain = 0x800 figure 40. energy register rollover time for full-scale power (minimum and maximum power gain) note that the energy register contents rolls over to full-scale negative (0x800000) and continues to increase in value when the power or energy flow is positivesee figure 40. conversely, if the power is negative, the energy register underflows to full- scale positive (0x7fffff) and continues to decrease in value. by using the interrupt enable register, the ade7169f16 can be configured to issue an ade interrupt to the 8052 core when the active energy register is half-full (positive or negative) or when an overflow or underflow occurs. integration time under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 1.22 s (5/clkin). with full-scale sinusoidal signals on the analog inputs and the wgain register set to 0x000, the average word value from each lpf2 is 0xccccdsee figure 37. the maximum positive value that can be stored in the internal 49-bit register is 2 48 or 0xffff,ffff,ffff before it overflows. the integration time under these conditions with wdiv = 0 is calculated as follows: time = xccccd 0 ffff ffff, xffff, 0 1.22 s = 409.6 s = 6.82 min (15) when wdiv is set to a value different from 0, the integration time varies, as shown in equation 16. wdiv time time wdiv = = 0 (16) active energy accumulation modes watt signed accumulation mode the ade7169f16 active energy default accumulation mode is a signed accumulation based on the active power information. watt positive-only accumulation mode the ade7169f16 is placed in positive-only accumulation mode by setting the poam bit in the accmode register (0x0f). in positive-only accumulation mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in figure 41. the cf pulse also reflects this accumulation method when in this mode. the default setting for this mode is off. detection of the transitions in the direction of power flow, and no-load threshold are active in this mode.
preliminary technical data ade7169f16 rev. prd | page 55 of 140 pos pos interrupt status registers neg apsign flag no-load threshold active power no-load threshold a ctive energy figure 41. energy accumulation in positive-only accumulation mode watt absolute accumulation mode the ade7169f16 is placed in absolute accumulation mode by setting the absam bit in the accmode register (0x0f). in absolute accumulation mode, the energy accumulation is done using the absolute active power, ignoring any occurrence of power below the no-load threshold, as shown in figure 42. the cf pulse also reflects this accumulation method when in this mode. the default setting for this mode is off. detection of the transitions in the direction of power flow, and no-load threshold are active in this mode. pos pos interrupt status registers neg apsign flag no-load threshold active power no-load threshold a ctive energy apnoload a pnoload figure 42. energy accumulation in absolute accumulation mode active energy pulse output ade7169f16 also provides all the circuitry to have a pulse output that frequency is proportional to active power C see active power calculation section. this pulse frequency output uses the calibrated signal after wgain and its behavior is consistent with the setting of the active energy accumulation mode in the accmode register (0x0f). the pulse output is active low and should be preferably connected to an led as shown on figure 53 . line cycle active energy accumulation mode in line cycle energy accumulation mode, the energy accumula- tion of the ade7169f16 can be synchronized to the voltage channel zero crossing so that active energy can be accumulated over an integral number of half line cycles. the advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. this eliminates any ripple in the energy calculation. energy is calculated more accurately and in a shorter time because the integration period can be shortened. by using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. in line cycle energy accumulation mode, the ade7169f16 accumulates the active power signal in the lwatthr register for an integral number of line cycles, as shown in figure 44. the number of half line cycles is specified in the lincyc register. the ade7169f16 can accumulate active power for up to 65,535 half line cycles. because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumu- lation cycle the cycend flag in the interrupt status register 3 sfr (mirqsth, 0xde) is set. if the cycend enable bit in the interrupt enable register 3 sfr (mirqenh, 0xdb) is set, the 8052 core has a pending ade interrupt. the ade interrupt stays active until the cycend status bit is clearedsee energy measurement interrupts section. another calibration cycle will start as soon as the cycend flag is set. if the lwatthr register is not read before a new cycend flag is set, the lwatthr register will be overwritten by a new value. when a new half line cycles is written in linecyc register, the lwatthr register is reset and a new accumulation start at the next zero-crossing. the number of half line cycles is then counted until lincyc is reached . this implementation provides a valid measurement at the first cycend interrupt after writing to the lincyc register C see figure 43. the line active energy accumulation uses the same signal path as the active energy accumulation. the lsb size of these two registers is equivalent.
ade7169f16 preliminary technical data rev. prd | page 56 of 140 linecyc value cycend irq lwatthr register figure 43. energy accumulation when linecyc changed from equations 13 and 18, e ( t ) = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? nt nt f vi dt vi 0 2 0 cos 9 . 8 1 (2 ft ) dt (20) where: n is an integer. t is the line cycle period. since the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. therefore, e = nt vidt 0 + 0 (21) e ( t ) = vint (22) wdiv[7:0] wattos[15:0] wgain[11:0] lpf1 + + lwatthr [23:0] accumulate active energy in internal register and update the lwatthr register at the end of lincyc half line cycles output from lpf2 from voltage channel adc 23 0 lincyc [15:0] 48 0 % zero cross detection calibration control to digital to frequency converter figure 44. line cycle active energy accumulation note that in this mode, the 16-bit lincyc register can hold a maximum value of 65,535. in other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. at 60 hz line frequency, it translates to a total duration of 65,535/120 hz = 546 seconds. reactive power calculation reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90. the resulting waveform is called the instantaneous reactive power signal. equation 25 gives an expression for the instanta- neous reactive power signal in an ac system when the phase of the current channel is shifted by +90. v ( t ) = ) sin( 2 + t v (23) i ( t ) = ) sin( 2 t i ? ? ? ? ? ? + = 2 sin 2 ) ( t i t i (24) where: is the phase difference between the voltage and current channel. v is the rms voltage. i is the rms current. q ( t ) = v ( t ) i ( t ) (25)
preliminary technical data ade7169f16 rev. prd | page 57 of 140 q ( t ) = vi sin ( ) + vi sin ) 2 ( + t the average reactive power over an integral number of lines (n) is given in equation 26. = = nt vi dt t q nt q 0 ) sin( ) ( 1 (26) where: t is the line cycle period. q is referred to as the reactive power. note that the reactive power is equal to the dc component of the instantaneous reactive power signal q (t) in equation 25. this is the relationship used to calculate reactive power in the ade7169f16. the instantaneous reactive power signal q (t) is generated by multiplying voltage and current channels. in this case, the phase of current channel is shifted by +90. the dc component of the instantaneous reactive power signal is then extracted by a low-pass filter in order to obtain the reactive power information C see figure 45. in addition, the phase shifting filter has a non-unity magnitude response. because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. the effect of harmonics is largely ignored in the reactive power calculation. note that because of the magnitude characteristic of the phase shifting filter, the weight of the reactive power is slightly different from the active power calculation C see energy register scaling. the frequency response of the lpf in the reactive signal path is identical to that of the lpf2 used in the average active power calculation. since lpf2 does not have an ideal brick wall frequency responsesee figure 38, the reactive power signal has some ripple due to the instantaneous reactive power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated to calculate energysee the reactive power calculation section. the reactive power signal can be read from the waveform register by setting the wavmode register (0x0d) and setting the wfsm bit in the interrupt enable register 3 sfr (mirqenh, 0xdb). like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps. reactive power gain calibration figure 45 shows the signal processing chain for the reactive power calculation in the ade7169f16. as explained, the reactive power is calculated by low-pass filtering the instantaneous reactive power signal. note that when reading the waveform samples from the output of lpf2, the gain of the reactive energy can be adjusted by using the multiplier and var gain register (vargain[11:0]). the gain is adjusted by writing a twos complement 12-bit word to the var gain register. equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 12 2 1 re vargain power active vargain output (11) the resolution of the vargain register is the same as the wgain register C see active power gain calibration section. vargain can be used to calibrate the reactive power (or energy) calculation in the ade7169f16. reactive power offset calibration the ade7169f16 also incorporates a reactive power offset register (varos[15:0]). this is a signed twos complement 16- bit register that can be used to remove offsets in the reactive power calculationsee figure 45. an offset could exist in the reactive power calculation due to crosstalk between channels on the pcb or in the ic itself. the offset calibration allows the contents of the reactive power register to be maintained at 0 when no power is being consumed. the 256 lsbs (varos = 0x100) written to the reactive power offset register are equivalent to 1 lsb in the waveform sample register. sign of reactive power calculation note that the average reactive power is a signed calculation. the phase shift filter has C90 phase shift when the integrator is enabled, and +90 phase shift when the integrator is disabled. table 41 summarizes the relationship between the phase differ- ence between the voltage and the current and the sign of the resulting var calculation. table 41. sign of reactive power calculation angle integrator sign between 0 to 90 off positive between C90 to 0 off negative between 0 to 90 on positive between C90 to 0 on negative reactive power sign detection the ade7169f16 detects a change of sign in the reactive power. the varsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) record when a change of sign according to bit varsign in the accmode register (0x0f) has occurred. if the varsign bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), the 8052 core has a pending ade interrupt. the ade interrupt stays active until the varsign status bit is clearedsee energy measurement interrupts section. when varsign in the accmode register (0x0f) is cleared
ade7169f16 preliminary technical data rev. prd | page 58 of 140 (default), the varsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when a transition from positive to negative reactive power has occurred. when varsign in the accmode register (0x0f) is set, the varsign flag in the interrupt status register 1 sfr (mirqstl, 0xdc) will be set when a transition from negative to positive reactive power has occurred. reactive power no-load detection the ade7169f16 includes a no-load threshold feature on the reactive energy that eliminates any creep effects in the meter. the ade7169f16 accomplishes this by not accumulating reactive energy if the multiplier output is below the no-load threshold. when the reactive power is below the no-load threshold, the rnoload flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set. if the rnoload bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), the 8052 core has a pending ade interrupt. the ade interrupt stays active until the rnoload status bit is clearedsee energy measurement interrupts section. the no-load threshold level is selectable by setting bits rnoload in the nlmode register (0x0e). setting these bits to 0b00 disable the no-load detection and setting them to 0b01, 0b10 or 0b11 set the no-load detection threshold to 0.015%, 0.0075% and 0.0037% of the full-scale output frequency of the multiplier respectively. vargain[11:0] vardiv[7:0] lpf2 current channel voltage channel output lpf2 time (nt) 5 clkin t reactive power signal + + varhr[23:0] outputs from the lpf2 are accumulated (integrated) in the internal reactive energy register upper 24 bits are accessible through varhr[23:0] register 23 0 48 0 waveform register values % varos[15:0] 2 6 sgn 2 5 2 -6 2 -7 2 -8 + + for wavef0rm sampling hpf 90 phase shifting filter 2 phcal[7:0] to digital to frequency converter figure 45. ade7169f16 reactive energy calculation reactive energy calculation as for active energy, the ade7169f16 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in an internal non-readable 49-bit energy register. the reactive energy register (varhr[23:0]) represents the upper 24 bits of this internal register. the discrete time sample period ( t ) for the accumulation register in the ade7169f16 is 1.22s (5/mclk). as well as calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. figure 45 shows this discrete time integration or accumulation. the reactive power signal in the waveform register is continuously added to the internal reactive energy register. the reactive energy accumulation depends on the setting of the savarm and absvarm bits in the accmode register (0x0f). when both bits are cleared, the addition is signed and therefore negative energy is subtracted from the reactive energy contents. when both bits are set, the ade7169f16 is set to be in the more restrictive mode, the absolute accumulation mode. when savarm bit in the accmode register (0x0f) is set, the reactive power is accumulated depending on the sign of the active power. when active power is positive, the reactive power is added as it is to the reactive energy register. when active power is negative, the reactive power is subtracted to the reactive energy accumulator C see var anti-tamper accumulation mode. when absvarm bit in the accmode register (0x0f) is set, the absolute reactive power is used for the reactive energy accumulationsee the var absolute accumulation mode section. the output of the multiplier is divided by vardiv. if the value in the vardiv register is equal to 0, then the internal reactive
preliminary technical data ade7169f16 rev. prd | page 59 of 140 energy register is divided by 1. vardiv is an 8-bit unsigned register. after dividing by vardiv, the reactive energy is accumulated in a 49-bit internal energy accumulation register. the upper 24 bits of this register are accessible through a read to the reactive energy register (varhr[23:0]). a read to the rvarhr register returns the content of the varhr register and the upper 24 bits of the internal register are cleared. as shown in figure 45, the reactive power signal is accumulated in an internal 49-bit signed register. the reactive power signal can be read from the waveform register by setting the wavmode register (0x0d) and setting the wfsm bit in the interrupt enable register 3 sfr (mirqenh, 0xdb). like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps. figure 40 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. these curves also apply for the reactive energy accumulation note that the energy register contents rolls over to full-scale negative (0x800000) and continues to increase in value when the power or energy flow is positive. conversely, if the power is negative, the energy register underflows to full-scale positive (0x7fffff) and continues to decrease in value. by using the interrupt enable register, the ade7169f16 can be configured to issue an ade interrupt to the 8052 core when the reactive energy register is half-full (positive or negative) or when an overflow or underflow occurs. integration time under steady load as mentioned in the active energy section, the discrete time sample period (t) for the accumulation register is 1.22 s (5/clkin). with full-scale sinusoidal signals on the analog inputs and the vargain and vardiv registers set to 0x000, the integration time before the reactive energy register overflows is calculated as follows: time = xccccd 0 ffff ffff, xffff, 0 1.22 s = 409.6 s = 6.82 min (15) when vardiv is set to a value different from 0, the integration time varies, as shown in equation 16. vardiv time time wdiv = = 0 (16) reactive energy accumulation modes var signed accumulation mode the ade7169f16 reactive energy default accumulation mode is a signed accumulation based on the reactive power information. var anti-tamper accumulation mode the ade7169f16 is placed in var anti-tamper accumulation mode by setting the savarm bit in the accmode register (0x0f). in this mode, the reactive power is accumulated depending on the sign of the active power. when active power is positive, the reactive power is added as it is to the reactive energy register. when active power is negative, the reactive power is subtracted to the reactive energy accumulator C see figure 46. the cf pulse also reflects this accumulation method when in this mode. the default setting for this mode is off. transitions in the direction of power flow, and no-load threshold are active in this mode. pos pos interrupt status registers neg apsign flag no-load threshold active power no-load threshold reactive energ y no-load threshold reactive power no-load threshold figure 46. reactive energy accumulation in anti-tamper accumulation mode var absolute accumulation mode the ade7169f16 is placed in absolute accumulation mode by setting the absvarm bit in the accmode register (0x0f). in absolute accumulation mode, the reactive energy accumulation is done using the absolute reactive power, ignoring any occurrence of power below the no-load threshold, as shown in figure 42 for the active energy. the cf pulse also reflects this accumulation method when in this mode. the default setting for this mode is off. transitions in the direction of power flow, and no-load threshold are active in this mode.
ade7169f16 preliminary technical data rev. prd | page 60 of 140 reactive energ y no-load threshold reactive power no-load threshold figure 47. reactive energy accumulation in absolute accumulation mode reactive energy pulse output ade7169f16 also provides all the circuitry to have a pulse output those frequency is proportional to reactive power C see energy-to-frequency conversion section. this pulse frequency output uses the calibrated signal after vargain and its behavior is consistent with the setting of the reactive energy accumulation mode in the accmode register (0x0f). the pulse output is active low and should be preferably connected to an led as shown on figure 53 . line cycle reactive energy accumulation mode in line cycle energy accumulation mode, the energy accumula- tion of the ade7169f16 can be synchronized to the voltage channel zero crossing so that reactive energy can be accumulated over an integral number of half line cycles. the advantage of this mode is similar to the ones explained in the active energy line cycle accumulation mode C see line cycle active energy accumulation mode section. in line cycle energy accumulation mode, the ade7169f16 accumulates the reactive power signal in the lvarhr register for an integral number of line cycles, as shown in figure 48. the number of half line cycles is specified in the lincyc register. the ade7169f16 can accumulate active power for up to 65,535 half line cycles. because the reactive power is integrated on an integral number of line cycles, at the end of a line cycle energy accumulation cycle the cycend flag in the interrupt status register 3 sfr (mirqsth, 0xde). if the cycend enable bit in the interrupt enable register 3 sfr (mirqenh, 0xdb) is set, the 8052 core has a pending ade interrupt. the ade interrupt stays active until the cycend status bit is clearedsee energy measurement interrupts section. another calibration cycle will start as soon as the cycend flag is set. if the lvarhr register is not read before a new cycend flag is set, the lvarhr register will be overwritten by a new value. as for lwatthr, when a new half line cycles is written in lincyc register, the lvarhr register is reset and a new accumulation start at the next zero-crossing. the number of half line cycles is then counted until lincy is reached. this implementation provides a valid measurement at the first cycend interrupt after writing to the lincyc register. the line reactive energy accumulation uses the same signal path as the reactive energy accumulation. the lsb size of these two registers is equivalent. vardiv[7:0] varos[15:0] vargain[11:0] lpf1 + + lvarhr [23:0] accumulate reactive energy in internal register and update the lvarhr register at the end of lincyc half line cycles output from lpf2 from voltage channel adc 23 0 lincyc [15:0] 48 0 % zero cross detection calibration control to digital to frequency converter figure 48 line cycle . reactive energy accumulation mode apparent power calculation the apparent power is defined as the maximum power that can be delivered to a load. v rms and i rms are the effective voltage and current delivered to the load; the apparent power (ap) is defined
preliminary technical data ade7169f16 rev. prd | page 61 of 140 as v rms i rms . equation 28 gives an expression of the instantaneous power signal in an ac system with a phase shift. () 2 sin( ) rms vt v t = i ( t ) = ) sin( 2 + t i rms (27) ) ( ) ( ) ( t i t v t p = p ( t ) = ) 2 cos( ) cos( + ? t i v i v rms rms rms rms (28) the apparent power is defined as v rms i rms . this expression is independent from the phase angle between the current and the voltage. figure 49 illustrates the signal processing in each phase for the calculation of the apparent power in the ade7169f16. v rms i rms 0x1a36e2 app a rent power signal (p) current rms signal ? i(t) voltage rms signal ? v(t) multiplier 0x00 0x1cf68c 0x00 0x1cf68c vagain to digital to frequency converter figure 49. apparent power signal processing the apparent power signal can be read from the waveform register by setting the wavmode register (0x0d) and setting the wfsm bit in the interrupt enable register 3 sfr (mirqenh, 0xdb). like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 ksps, 14 ksps, 7 ksps, or 3.5 ksps. the gain of the apparent energy can be adjusted by using the multiplier and vagain register (vagain[11:0]). the gain is adjusted by writing a twos complement, 12-bit word to the vagain register. equation 29 shows how the gain adjustment is related to the contents of the vagain register. ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 12 2 1 vagain power apparent in outputvaga (29) for example, when 0x7ff is written to the vagain register, the power output is scaled up by 50%. 0x7ff = 2047d, 2047/2 12 = 0.5. similarly, 0x800 = C2047d (signed twos complement) and power output is scaled by C50%. each lsb represents 0.0244% of the power output. the apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ade7169f16. apparent power offset calibration each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms valuesee current channel rms calculation and voltage channel rms calculation sections. the voltage and current channels rms values are then multiplied together in the apparent power signal processing. since no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. the offset compensation of the apparent power measurement is done by calibrating each individual rms measurement. apparent energy calculation the apparent energy is given as the integral of the apparent power. = dt t power apparent energy apparent ) ( (30) the ade7169f16 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. the apparent energy register (vahr[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 31 expresses the relationship ? ? ? ? ? ? ? ? ? ? = = 0 0 ) ( n t t nt power apparent lim energy apparent (31) where: n is the discrete time sample number. t is the sample period. the discrete time sample period (t) for the accumulation register in the ade7169f16 is 1.22 s (5/mclk). figure 50 shows this discrete time integration or accumulation. the apparent power signal is continuously added to the internal register. this addition is a signed addition even if the apparent energy remains theoretically always positive. the 49 bits of the internal register are divided by vadiv. if the value in the vadiv register is 0, then the internal apparent energy register is divided by 1. vadiv is an 8-bit unsigned register. the upper 24 bits are then written in the 24-bit apparent energy register (vahr[23:0]). rvahr register (24 bits long) is provided to read the apparent energy. this register is reset to 0 after a read operation.
ade7169f16 preliminary technical data rev. prd | page 62 of 140 vadiv apparent power + + v ahr[23:0] apparent power are accumulated (integrated) in the apparent energy register 23 0 48 0 48 0 % time (nt) t apparent power signal = p figure 50. ade7169f16 apparent energy calculation note that the apparent energy register is unsigned. by setting the vaehf and vaeof bits in the interrupt enable register 2 sfr (mirqenm, 0xda), the ade7169f16 can be configured to issue an ade interrupt to the 8052 core when the apparent energy register is half full or when an overflow occurs. the half full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register. integration times under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 1.22 s (5/mclk). with full-scale sinusoidal signals on the analog inputs and the vagain register set to 0x000, the average word value from apparent power stage is 0x1a36e2see the section. the maximum value that can be stored in the apparent energy register before it overflows is 2 24 or 0xff,ffff. the average word value is added to the internal register, which can store 2 48 or 0xffff,ffff,ffff before it overflows. therefore, the integration time under these conditions with vadiv = 0 is calculated as follows: time = 055 xd 0 ffff ffff, xffff, 0 1.22 s = 199 s = 3.33 min (32) when vadiv is set to a value different from 0, the integration time varies, as shown in equation 33. time = time wdiv = 0 vadiv (33) apparent energy pulse output ade7169f16 also provides all the circuitry to have a pulse output those frequency is proportional to apparent power C see energy-to-frequency conversion section. this pulse frequency output uses the calibrated signal after vagain. this output can also be used to output a pulse those frequency is proportional to irms. the pulse output is active low and should be preferably connected to an led as shown on figure 53 . line apparent energy accumulation the ade7169f16 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. by using the on-chip zero-crossing detection, the ade7169f16 accumulates the apparent power signal in the lvahr register for an integral number of half cycles, as shown in figure 51. the line apparent energy accumulation mode is always active. the number of half line cycles is specified in the lincyc register, which is an unsigned 16-bit register. the ade7169f16 can accumulate apparent power for up to 65535 combined half cycles. because the apparent power is integrated on the same integral number of line cycles as the line active and reactive energy register, these values can be compared easily. the energies are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. at the end of an energy calibration cycle, the cycend flag in the interrupt status register 3 sfr (mirqsth, 0xde) is set. if the cycend enable bit in the interrupt enable register 3 sfr (mirqenh, 0xdb) is enabled, the 8052 core has a pending ade interrupt. as for lwatthr, when a new half line cycles is written in linecyc register, the lvahr register is reset and a new accumulation start at the next zero-crossing. the number of half line cycles is then counted until lincy is reached. this implementation provides a valid measurement at the first cycend interrupt after writing to the lincyc register. the line apparent energy accumulation uses the same signal path as the apparent energy accumulation. the lsb size of these two registers is equivalent.
preliminary technical data ade7169f16 rev. prd | page 63 of 140 vadiv[7:0] lpf1 + + lvahr [23:0] lvahr register is updated every lincyc zero crossings with the total apparent energy during that duration apparent power from voltage channel adc 23 0 lincyc [15:0] 48 0 % zero-crossing detection calibration control figure 51. ade7169f16 line cycle apparent energy accumulation apparent power no-load detection the ade7169f16 includes a no-load threshold feature on the apparent energy that eliminates any creep effects in the meter. the ade7169f16 accomplishes this by not accumulating energy if the multiplier output is below the no-load threshold. when the apparent power is below the no-load threshold, the vanoload flag in the interrupt status register 1 sfr (mirqstl, 0xdc) is set. if the vanoload bit is set in the interrupt enable register 1 sfr (mirqenl, 0xd9), the 8052 core has a pending ade interrupt. the ade interrupt stays active until the apnoload status bit is clearedsee energy measurement interrupts section. the no-load threshold level is selectable by setting bits vanoload in the nlmode register (0x0e). setting these bits to 0b00 disable the no-load detection and setting them to 0b01, 0b10 or 0b11 set the no-load detection threshold to 0.030%, 0.015% and 0.0075% of the full-scale output frequency of the multiplier respectively. this no-load threshold can also be applied to the irms pulse output when selected. the level of no-load threshold is the same as for the apparent energy in this case. energy-to-freque ncy conversion ade7169f16 also provides two energy-to-frequency conversions for calibration purposes. after initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. one convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the active, reactive, apparent power or irms under steady load conditions. this output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. figure 52 illustrates the energy-to-frequency conversion in the ade7169f16. cfx pulse output cfxnum cfxden dfc var va irms cfxsel[1:0] watt varmscfcon mode2 register 0x0c figure 52. ade7169f16 energy-to-frequency conversion two digital-to-frequency converters (dfc) are used to generate the pulsed outputs. when wdiv =0 or 1, the dfc generates a pulse each time 1 lsb in the energy register is accumulated. an output pulse is generated when cfxden/cfxnum number of pulses are generated at the dfc output. under steady load conditions, the output frequency is proportional to the active, reactive, apparent power or irms depending on the cfxsel bit in the mode2 register (0x0c). both pulse outputs can be enabled or disabled by clearing or setting respectively bits discf1 and discf2 in the mode1 register (0x0b). both pulse outputs set a separate flag in the interrupt status register 2 sfr (mirqstm, 0xdd), cf1 and cf2. if cf1 and cf2 enable bits in the interrupt enable register 2 sfr (mirqenm, 0xda) are set, the 8052 core has a pending ade interrupt. the ade interrupt stays active until the cf1 or cf2 status bits are clearedsee energy measurement interrupts section. pulse output configuration the two pulse outputs circuitry have separate configuration bits in the mode2 register (0x0c). setting cfxsel bits to 0b00, 0b01 or 0b1x configure the dfc to create a pulse output
ade7169f16 preliminary technical data rev. prd | page 64 of 140 proportional to active power, reactive power, or apparent/irms respectively. the selection between irms and apparent power is done by the varmscfcon bit in the mode2 register (0x0c). with this selection, cf2 cannot be proportional to apparent power if cf1 is proportional to irms and vice-versa. pulse output characteristic the pulse output for both dfc stays low for 90ms if the pulse period is larger than 180ms (5.56hz). if the pulse period is smaller than 180ms, the duty cycle of the pulse output is 50%. the pulse output is active low and should be preferably connected to an led as shown on figure 53 . cf v dd figure 53. cf pulse output the maximum output frequency, with ac input signals at full scale and cfxnum = 0x00 and cfxden = 0x00, is approximately 21.1 khz. the ade7169f16 incorporates two registers, cfxnum[15:0] and cfxden[15:0] per dfc, to set the cfx frequency. these are unsigned 16-bit registers, which can be used to adjust the cfx frequency to a wide range of values. these frequency- scaling registers are 16-bit registers, which can scale the output frequency by 1/2 16 to 1 with a step of 1/2 16 . if the value 0 is written to any of these registers, the value 1 would be applied to the register. the ratio cfxnum / cfxden should be smaller than 1 to ensure proper operation. if the ratio of the registers cfxnum / cfxden is greater than 1, the register values would be adjusted to a ratio of 1. for example, if the output frequency is 1.562 khz while the contents of cfxden are 0 (0x000), then the output frequency can be set to 6.1 hz by writing 0xff to the cfxden register. energy register scaling the ade7169f16 provides measurements of active, reactive, and apparent energies that use separate paths and filtering for calculation. the difference in data paths can result in small differences in lsb weight between active, reactive and apparent energy registers. these measurements are internally compensated so the scaling is nearly one to one. the relationship between the registers is show in table 42. in table 43, the relationship between wattgain, vargain and vagain is given. these relationships can be used for calibration and simplify the adjustment of var and va gains. as var and va gains can be deducted from wgain, there is no need to do reactive or apparent gai adjustment. table 42. energy registers scaling line frequency = 50hz line frequency = 60hz integrator off var = 0.9952 watt var = 0.9949 wat t va = 0.9978 watt va = 1.0015 wat t integrator on var = 0.9997 watt var = 0.9999 wat t va = 0.9977 watt va = 1.0015 wat t table 43. gain compensation adjustments line frequency = 50hz line frequency = 60hz integrator off vargain = 19.76 + wgain/0.9952 vargain = 21 + wgain/0.9949 vagain = 9.03 + wgain/0.9978 vagain = -60.53 + wgain/1.0015 integrator on vargain = 1.23 + wgain/0.9997 vargain = 0.41 + wgain/0.9999 vagain = 9.44 + wgain/0.9977 vagain = -60.53 + wgain/1.0015 energy measurement interrupts the energy measurement part of the ade7169f16 has its own interrupt vector for the 8052 core C vector address 0x004b C see interrupt vectors section. the bits set in the interrupt enable register 1 sfr (mirqenl, 0xd9), interrupt enable register 2 sfr (mirqenm, 0xda), and interrupt enable register 3 sfr (mirqenh, 0xdb) enables the energy measurement interrupts that are allowed to interrupt the 8052 core. if an event is not enabled, it cannot create a system interrupt. the ade interrupt stays active until the status bit that has created the interrupt is cleared. two methods can be used to clear the ade interrupt: - when bit 6 (adeiautclr) of the power management interrupt enable sfr (ipsme, 0xec) is set, all the status bits of the ade irq status register (1, 2 or 3) are cleared when the register is read. - when bit 6 (adeiautclr) of the power management
preliminary technical data ade7169f16 rev. prd | page 65 of 140 interrupt enable sfr (ipsme, 0xec) is cleared, a status bit of the ade irq status register (1, 2 or 3) is cleared when a zero is written to this register bit.
preliminary technical data ade7169f16 rev. prd | page 66 of 140 temperature, battery and supply voltage measurements the ade7169f16 includes temperature measurements as well as battery and supply voltage measurements. these measurements enable many forms of compensation. the temperature and supply voltage measurements can be used to compensate external circuitry. the rtc can be calibrated over temperature to ensure that it doesnt drift. supply voltage measurements allow the lcd contrast to be maintained despite variations in voltage. battery measurements allow low battery detection to be performed. all adc measurements are configured through the sfr detailed in table 44. the temperature, battery and supply voltage measurements can be configured to still be functional in psm1 and psm2. this is done bit setting bit rtcen in the rtc configuration sfr (timecon, 0xa1). maintaining the temperature measurement active ensures that it is not necessary to wait for the temperature measurement to settle before using it for compensation. table 44. temperature, battery and supply voltage measurement sfrs sfr address (hex) r/w name description 0xf9 r/w strbper strobing period configuration 0xf3 r/w diffprog temperature and supply delta configuration 0xd8 r/w adcgo adc start configuration 0xfa r/w batvth battery threshold configuration 0xef r/w vswadc vsw adc value 0xdf r/w batadc battery adc value 0xd7 r/w tempadc temperature adc value table 45. peripheral adc strobe period sfr (strbper, 0xf9) note: the strobing option only work when the rtcen bi t in rtc configuration sfr (timecon, 0xa1) is set. bit location bit mnemonic default value description 7-6 reserved - reserved period for background supply voltage measurements vsw_period[1:0] 0 0 no vsw measurement 0 1 8 minutes 1 0 2 minutes 5-4 vsw_period[1:0] 0 1 1 1 minute period for background battery level measurements batt_period[1:0] 0 0 no battery measurement 0 1 16 minutes 1 0 4 minutes 3-2 batt_period[1:0] 0 1 1 1 minute period for background temperature measurements temp_period[1:0] 0 0 no temperature measurements 0 1 8 minutes 1-0 temp_period[1:0] 0 1 0 2 minutes
preliminary technical data ade7169f16 rev. prd | page 67 of 140 1 1 1 minute table 46. temperature and supply delta sfr (diffprog, 0xf3) bit location bit mnemonic default value description 7-6 reserved 0 reserved difference threshold between last te mperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052 temp_diff[2:0] 0 0 0 no interrupt 0 0 1 0 1 0 < 1 lsb ( 0.8 c) 0 1 1 1 0 0 1 lsb ( 1.6 c) 1 0 1 1 1 0 2 lsb ( 3.2 c) 5-3 temp_diff[2:0] 0 1 1 1 every temperature measurement difference threshold between last su pply voltage measurement interrupting 8052 and new temperature measurement that should interrupt 8052 vsw_diff[2:0] 0 0 0 no interrupt 0 0 1 0 1 0 0 1 1 < 1 lsb ( 15mv) 1 0 0 1 0 1 1 1 0 1 lsb ( 120 mv) 2-0 vsw_diff[2:0] 0 1 1 1 every vsw measurement table 47. start adc measurement sfr (adcgo, 0xd8) bit location bit addr. bit name default value description 7 0xdf pllack 0 set this bit to clear the pll fault bi t, pll_flt in the periph register. a pll fault is generated if a reset was caused because the pll lost lock. 6-3 0xde C 0xdb reserved 0 reserved 2 0xda vadc 0 set this bit to initiate a supply vo ltage measurement. this bit will be cleared when the measurement requ est is received by the adc. 1 0xd9 tadc 0 set this bit to initiate a temperature measurement. this bit will be cleared when the measurement request is received by the adc. 0 0xd8 btadc 0 set this bit to initiate a battery measur ement. this bit will be cleared when the measurement request is received by the adc. table 48. battery detection threshold sfr (batvth, 0xfa) bit location bit mnemonic default value description 7-0 batvth 0 the battery adc value is compared to this register, the battery threshold register. if batadc is lower than the threshold, an interrupt is generated.
ade7169f16 preliminary technical data rev. prd | page 68 of 140 table 49. vsw adc value sfr (vswadc, 0xef) bit location bit mnemonic default value description 7-0 vswadc 0 the vsw adc value in this register is updated when an adc interrupt occurs. table 50. battery adc value sfr (batadc, 0xdf) bit location bit mnemonic default value description 7-0 batadc 0 the battery adc value in this register is updated when an adc interrupt occurs. table 51. temperature adc value sfr (tempadc, 0xd7) bit location bit mnemonic default value description 7-0 tempadc 0 the temperature adc value in this register is updated when an adc interrupt occurs. temperature measurement to provide a digital temperature measurement, the ade7169f16 includes a dedicated adc. an 8-bit temperature adc value sfr (tempadc, 0xd7) holds the results of the temperature conversion. the resolution of the temperature measurement is tbd ? c/lsb. there are two ways to initiate a temperature conversion: - single temperature measurement - background temperature measurements single temperature measurement set the temp_adc_go bit in the start adc measurement sfr (adcgo, 0xd8) to get a temperature measurement. an interrupt will be generated when the conversion is done and the temperature measurement is available in the temperature adc value sfr (tempadc, 0xd7). background temperature measurements background temperature measurements are disabled by default. to configure the background temperature measurement mode, set a temperature measurement interval in the peripheral adc strobe period sfr (strbper, 0xf9). then temperature measurements will be performed periodically in the background C see table 45. when a temperature conversion completes, the new temperature adc value is compared to the last temperature adc value that created an interrupt. if the absolute difference between the two values is greater than the setting in the temp_diff bits in the temperature and supply delta sfr (diffprog, 0xf3), a tempadc interrupt is generated. this allows temperature measurements to take place completely in the background, only requiring mcu activity if the temperature has changed more than a configurable delta. to set up background temperature measurements: 1. initiate a single temperature measurement by setting the temp_adc_go bit in the start adc measurement sfr (adcgo, 0xd8). 2. upon completion of this measurement, configure the temp_diff[2:0] bits to establish the change in temperature that will trigger an interrupt. 3. set up the interval for background temperature measurements by configuring the temp_period[1:0] bits. temperature adc in psm1 and psm2 depending on the operating mode of the ade7169f16, a temperature conversion is initiated only by certain actions: psm0: in this operating mode, the 8052 is active. temperature measurements are available in the background measurement mode and by initiating a single measurement. psm1: in this operating mode, the 8052 is active and the part is powered from battery. single temperature measurements can be initiated by setting the temp_adc_go bit in the start adc measurement sfr (adcgo, 0xd8). background temperature measurements are not available. psm2: in this operating mode, the 8052 is not active. temperature conversions are available through the background measurement mode only. the temperature adc value sfr (tempadc, 0xd7) is updated with a new value only when a temperature adc interrupt occurs.
preliminary technical data ade7169f16 rev. prd | page 69 of 140 temperature adc interrupt the temperature adc can generate an adc interrupt when at least one of the following conditions occurs: - the difference between the new temperature adc value and the last temperature adc value generating an adc interrupt is larger than the value set in the temp_diff bits. - the temperature adc conversion, initiated by setting start adc measurement sfr (adcgo, 0xd8), is finished. when the adc interrupt occurs, a new value is available in the temperature adc value sfr (tempadc, 0xd7). note that there is no flag associated with this interrupt. battery measurement to provide a digital battery measurement, the ade7169f16 includes a dedicated adc. the battery measurement is available in an 8-bit sfr (battery adc value sfr (batadc, 0xdf). the battery measurement has a resolution of 15 mv/lsb. a battery conversion can be initiated by two methods: - single battery measurement - background battery measurements single battery measurement set the batt_adc_go bit in the start adc measurement sfr (adcgo, 0xd8) to get a battery measurement. an interrupt will be generated when the conversion is done and the battery measurement is available in the battery adc value sfr (batadc, 0xdf). background battery measurements to configure background measurements for the battery, establish a measurement interval in the peripheral adc strobe period sfr (strbper, 0xf9). then battery measurements will be performed periodically in the background C see table 45. when a battery conversion completes, the battery adc value is compared to the low battery threshold, established in the battery detection threshold sfr (batvth, 0xfa). if it is below this threshold, a low battery flag is set. this low battery flag is the battflag bit in the power management interrupt flag sfr (ipsmf, 0xf8), used for power supply monitoring. this low battery flag can be enabled to generate the psm interrupt by setting the ebatt bit in the power management interrupt enable sfr (ipsme, 0xec). this method allows battery measurements to take place completely in the background, only requiring mcu activity if the battery drops below a user specified threshold. to set up background battery measurements: 1. configure the battery detection threshold sfr (batvth, 0xfa) to establish a low battery threshold. if the batadc measurement is below this threshold, the battflag in the power management interrupt flag sfr (ipsmf, 0xf8) will be set. 2. set up the interval for background battery measurements by configuring the batt_period[1:0] bits. battery adc in psm1 and psm2 depending on the operating mode, a battery conversion is initiated only by certain actions: psm0: in this operating mode, the 8052 is active. battery measurements are available in the background measurement mode and by initiating a single measurement. psm1: in this operating mode, the 8052 is active and the part is powered from battery. single battery measurements can be initiated by setting the batt_adc_go bit in the start adc measurement sfr (adcgo, 0xd8). background battery measurements are not available. psm2: in this operating mode, the 8052 is not active. battery conversions are available through the background measurement mode only. battery adc interrupt the battery adc can generate an adc interrupt when at least one of the following conditions occurs: - the new battery adc value is smaller than the value set in the battery detection threshold sfr (batvth, 0xfa), indicating a battery voltage loss. - a single battery measurement, initiated by setting the batt_adc_go bit, is finished. when the battery flag is set in the power management interrupt flag sfr (ipsmf, 0xf8), a new adc value is available in the battery adc value sfr (batadc, 0xdf). this battery flag can be enabled as a source of the psm interrupt to generate a psm interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the batt_adc_go bit is ready. the battery adc value sfr (batadc, 0xdf) is updated with a new value only when the battery flag is set in the power management interrupt flag sfr (ipsmf, 0xf8). supply voltage measurement to provide a digital supply voltage measurement, the ade7169f16 includes a dedicated adc. an 8-bit sfr (table 49. vsw adc value sfr (vswadc, 0xef)) holds the results of the conversion. the resolution of the supply voltage measurement is tbd v/lsb. there are two ways to initiate a supply voltage conversion: - single supply voltage measurement
ade7169f16 preliminary technical data rev. prd | page 70 of 140 - background supply voltage measurements single supply voltage measurement set the vsw_adc_go bit in the start adc measurement sfr (adcgo, 0xd8) to get a supply voltage measurement. an interrupt will be generated when the conversion is done and the supply voltage measurement is available in the table 49. vsw adc value sfr (vswadc, 0xef). background supply voltage measurements background supply voltage measurements are disabled by default. to configure the background supply voltage measurement mode, set a supply voltage measurement interval in the peripheral adc strobe period sfr (strbper, 0xf9). then supply voltage measurements will be performed periodically in the background C see table 45. when a supply voltage conversion completes, the new supply voltage adc value is compared to the last supply voltage adc value that created an interrupt. if the absolute difference between the two values is greater than the setting in the vsw_diff bits in the temperature and supply delta sfr (diffprog, 0xf3), a vsw adc flag is set. this vsw adc flag is the vswflag in the power management interrupt flag sfr (ipsmf, 0xf8), used for power supply monitoring. this vsw adc flag can be enabled to generate a psm interrupt by setting the evsw bit in the power management interrupt enable sfr (ipsme, 0xec). this method allows supply voltage measurements to take place completely in the background, only requiring mcu activity if the supply voltage has changed more than a configurable delta. to set up background supply voltage measurements: 1. initiate a single supply voltage measurement by setting the vsw_adc_go bit in the start adc measurement sfr (adcgo, 0xd8). 2. upon completion of this measurement, configure the vsw_diff[2:0] bits to establish the change in temperature that will set the vswflag in the power management interrupt flag sfr (ipsmf, 0xf8). 3. set up the interval for background supply voltage measurements by configuring the vsw_period[1:0] bits. supply voltage adc in psm1 and psm2 depending on the operating mode of the ade7169f16, a supply voltage conversion is initiated only by certain actions: psm0: in this operating mode, the 8052 is active. supply voltage measurements are available in the background measurement mode and by initiating a single measurement. psm1: in this operating mode, the 8052 is active and the part is powered from battery. single supply voltage measurements can be initiated by setting the temp_adc_go bit in the start adc measurement sfr (adcgo, 0xd8). background supply voltage measurements are not available. psm2: in this operating mode, the 8052 is not active. supply voltage conversions are available through the background measurement mode only. the supply voltage table 49. vsw adc value sfr (vswadc, 0xef) is updated with a new value only when a supply voltage adc interrupt occurs. supply voltage adc interrupt the supply voltage adc can generate an adc interrupt when at least one of the following conditions occurs: - the difference between the new supply voltage adc value and the last supply voltage adc value generating an adc interrupt is larger than the value set in the vsw_diff bits. - the supply voltage adc conversion, initiated by setting temp_adc_go, is finished. when the adc interrupt occurs, a new value is available in the vsw adc value sfr (vswadc, 0xef). note that there is no flag associated with this interrupt.
preliminary technical data ade7169f16 rev. prd | page 71 of 140 8052 mcu core architecture the ade7169f16 has an 8052 mcu core and uses the 8051 instruction set. some of the standard 8052 peripherals, such as the uart, have been enhanced. this section describes the standard 8052 core and enhancements that have been made to it in the ade7169f16. the special function register (sfr) space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only. it provides an interface between the cpu and all on-chip peripherals. a block diagram showing the programming model of the ade7169f16 via the sfr area is shown in figure 54. all registers except the program counter (pc), instruction register (ir) and the four general-purpose register banks reside in the sfr area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and all on-chip peripherals. other on-chip peripherals: serial i/o wdt timers battery adc temperature adc lcd driver rtc power management energy measurement 16-kbyte electrically reprogrammable nonvolatile flash/ee program/data memory 256 bytes xram ir pc 8051 compatible core stack register banks 256 bytes general purpose ram 128-byte special function register area figure 54: ade7169f16 block diagram mcu registers the registers used by the mcu are summarized hereafter. table 52. 8051 sfrs sfr address bit addressable description a 0xe0 yes accumulator b 0xf0 yes auxiliary math register psw 0xd0 yes program status word - see table 53 pcon 0x87 no power control register C see table 54 dpl 0x82 no data pointer lsbyte C see table 55 dph 0x83 no data pointer msbyte C see table 56 sp 0x81 no stack pointer lsb byte C see table 57 cfg 0xaf no configuration register C see table 58 table 53. program status word sfr (psw, 0xd0) bit location bit addr. bit name description 7 0xd7 cy carry flag. modified by add, addc, subb, mul, and div instructions. 6 0xd6 ac auxiliary carry flag. modifi ed by add, and addc instructions. 5 0xd5 f0 general-purpose flag availble to the user register bank select bits. rs1 rs0 selected bank 0 0 0 0 1 1 1 0 2 4-3 0xd4, 0xd3 rs1, rs0 1 1 3 2 0xd2 ov overflow flag. modified by ad d, addc, subb, mul and div instructions. 1 0xd1 f1 general-purpose flag availble to the user. 0 0xd0 p parity bit. the number of bits set in the a ccumulator added to the value of the parity bit will always be an even number.
ade7169f16 preliminary technical data rev. prd | page 72 of 140 table 54. program control sfr (pcon, 0x87) bit location default description 7 0 double baud rate control 6-0 0 reserved, should be left cleared table 55. data pointer low sfr (dpl, 0x82) bits default description 7-0 0 contain the low byte of the data pointer table 56. data pointer high sfr (dph, 0x83) bits default description 7-0 0 contain the high byte of the data pointer table 57. stack pointer sfr (sp, 0x81) bits default description 7-0 7 contain the 8 lsb of the pointer for the stack table 58. configuration sfr (cfg, 0xaf) bit location bit mnemonic description 7 reserved.. this bit should be left set for proper operation. enhanced uart enable bit 0 standard 8052 uart without enha nced error checking features 6 exten 1 enhanced uart with enhanced error chec kingsee the uart additional features section. synchronous communication selection bit 0 i2c port is selected for control of the shared i2c/spi pins and sfrs 5 scps 1 spi port is selected for control of the shared i2c/spi pins and sfrs 38khz modulation enable bit 0 38khz modulation is disabled. 4 mod38en 1 38khz modulation is enabled on the pins selected by th e mod38[7:0] bits in the ep_cfg sfr. 3-2 reserved xren[1] or xren[0] =1 enable movx instruction to us e 256 bytes of extended ram. 1-0 xren[1:0] xren[1] and xren[0] =0 disable movx instruction basic 8052 registers program counter (pc): the program counter holds the two byte address of the next instruction to be fetched. the pc is initialized with 0x00 at reset and is incremented after each instruction is performed. note that the amount that is added to the pc depends on the number of bytes in the instruction, so the increment can range from one to three bytes. the program counter is not directly accessible to the user but can be directly modified by call and jmp instructions that change which part of the program is active. instruction register (ir): the instruction register holds the opcode of the instruction being executed. the opcode is the binary code that results from assembling an instruction. this register is not directly accessible to the user. register banks: there are four banks containing 8 byte-wide registers each, for a total of 32 bytes of registers. these registers are convenient for temporary storage of mathematical operands. an instruction involving the accumulator and a register can be executed in 1 clock cycle as opposed to 2 clock cycles to perform an instruction involving the accumulator and a literal or a byte of general purpose ram. the register banks are located in the first 32 bytes of ram.
preliminary technical data ade7169f16 rev. prd | page 73 of 140 the active register bank is selected by the rs0 and rs1 bits in the program status word sfr (psw, 0xd0). accumulator: the accumulator is a working register, storing the results of many arithmetic or logical operations. the accumulator is used in more than half of the 8052 instructions where it is usually referred to as a. the status register (psw) constantly monitors the number of bits that are set in the accumulator to determine if it has even or odd parity. the accumulator is stored in the sfr space - see table 52. b register: the b register is used by the multiply and divide instructions, mul ab and div ab to hold one of the operands. since it isnt used for many instructions, it can be used as a scratchpad register like those in the register banks. the b register is stored in the sfr space - see table 52. program status word (psw): the psw register reflects the status of arithmetic and logical operations through carry, auxiliary carry and overflow flags. the parity flag reflects the parity of the contents of the accumulator, which can be helpful for communication protocols. the psw bits are described in table 53. the program status word sfr (psw, 0xd0) is bit addressable. data pointer (dptr): the data pointer is made up of two 8-bit registers: dph (high byte), and dpl (low byte). these provide memory addresses for internal code and data access. the dptr can be manipulated as a 16-bit register (dptr = dph, dpl), or as two independent 8-bit registers (dph, dpl) C see table 55 and table 56. the ade7169f16 supports dual data pointers. see the dual data pointers section. stack pointer (sp): the stack pointer keeps track of the current address of the top of the stack. to push a byte of data onto the stack, the stack pointer is incremented and the data is moved to the new top of the stack. to pop a byte of data off of the stack, the top byte of data is moved into the awaiting address and the stack pointer is decremented. the stack is a last in first out (lifo) method of data storage because the most recent addition to the stack is the first to come off it. the stack is utilized during call and ret instructions to keep track of the address to move into the pc when returning from the function call. the stack is also manipulated when vectoring for interrupts, to keep track of the prior state of the pc. the stack resides into the extended internal ram and the sp register holds the address of the stack into the externded ram. the advantage of this solution is that the stack is segregated to the extended internal ram. the use of the general purpose ram can be limited to data storing and the use of the extended internal ram limited to the stack pointer. this separation limits the chance of corruption of the data ram with the stack pointer overflowing in data ram. data can still be stored in extended ram by using the movx command. to change the default starting address for the stack, move a value into the stack pointer, sp. for example, to enable the extended stack pointer and initialize it at the beginning of the xram space, use this code: mov sp,#00h 256 bytes of on-chip data 256 bytes of ram (data) 00h ffh ffh data+stack 00h 256 bytes of on-chip x-ram figure 55. extended stack pointer operation standard 8052 sfrs the standard 8052 special function registers include the accumulator, b, psw, dptr and sp sfrs described in the basic 8052 registers section. the 8052 also defines standard timers, serial port interface, interrupts, i/o ports and power down modes. timer sfrs: the 8052 contains 3 16-bit timers, the identical timer0 and timer1 as well as a timer2. these timers can also function as event counters. timer2 has a capture feature where the value of the timer can be captured in two 8-bit registers upon the assertion of an external input signal - see table 93 and timers section. serial port sfrs: the full-duplex serial port peripheral requires two registers, one for setting up the baud rate and other communication parameters, and another byte for the transmit/receive buffer. the ade7169f16 also provides
ade7169f16 preliminary technical data rev. prd | page 74 of 140 enhanced serial port functionality with a dedicated timer for baud rate generation with a fractional divisor and additional error detection. see table 115 and uart serial interface section. interrupt sfrs: there is a two-tiered interrupt system standard in the 8052 core. the priority level for each interrupt source is individually selectable as high or low. the ade7169f16 enhances this interrupt system by creating in essence a third interrupt tier for a highest priority power supply management interrupt, psm - see interrupt system section. i/o port sfrs: the 8052 core supports four i/o ports, p0 through p3 where ports 0 and 2 are typically used for access to external code and data spaces. the ade7169f16, unlike standard 8052 products, provides internal nonvolatile flash memory so that an external code space is unnecessary. the on- chip lcd driver requires many pins, some of which are dedicated for lcd functionality and others that can be configured at lcd or general purpose i/o. due to the limited number of i/o pins, the ade7169f16 does not allow access to external code and data spaces. the ade7169f16 provides 20 pins that can be used for general purpose i/o. these pins are mapped to ports 0, 1 and 2 and are accessed through three bit-addressable 8052 sfrs p0, p1 and p2. another enhanced feature of the ade7169f16 is that the weak pull-ups standard on 8052 ports 1, 2 and 3 can be disabled to make open drain outputs, as is standard on port 0. the weak pull-ups can be enabled on a pin by pin basis. see the i/o ports section. power control register (pcon, 0x87): the 8052 core defines two power down modes; power down and idle. the ade7169f16 enhances the power control capability of the traditional 8052 mcu with additional power management functions. the powcon register is used to define power control specific functionality for the ade7169f16. the program control sfr (pcon, 0x87) is not bit addressable. see the power management section. the ade7169f16 provides many other peripherals not standard to the 8052 core. ? ade energy measurement dsp ? rtc ? lcd driver ? battery switchover/power management ? temp er ature a d c ? battery adc ? spi/i 2 c communication ? flash memory controller ? watchdo g ti me r memory overview the ade7169f16 contains three memory blocks: ? 16 kbytes of on-chip flash/ee program and data memory ? 256 bytes of general-purpose ram ? 256 bytes of internal extended ram (xram) the 256 bytes of general-purpose ram shares the upper 128 bytes of its address space with special function registers. all of the memory spaces are shown in figure 54. the addressing mode specifies which memory space to access. general purpose ram: general purpose ram resides in memory locations 0x00 through 0xff. it contains the register banks. 11 10 01 00 07h 0fh 17h 1fh 2fh 7fh 00h 08h 10h 18h 20h reset value of stack pointer 30h four banks of eight registers r0 to r7 bit-addressable (bit addresses) general-purpose area banks selected via bits in psw 04741-0-008 figure 56. lower 128 bytes of internal data memory addresses 0x80 through 0xff of general purpose ram are shared with the special function registers. the mode of addressing determines which memory space is accessed as shown in figure 57. accessible by direct addressing only accessible by indirect addressing only accessible by direct and indirect addressing general purpose ram special function registers (sfrs) 00h 7fh 80h ffh figure 57: general purpose ram and sfr memory address overlap
preliminary technical data ade7169f16 rev. prd | page 75 of 140 both direct and indirect addressing can be used to access general purpose ram from 0x00 through 0x7f but indirect addressing must be used to access general purpose ram with addresses in the range from 0x80 through 0xff because they share the same address space with the special function registers (sfrs). the 8052 core also has the means to access individual bits of certain addresses in the general purpose ram and special function memory spaces. the individual bits of general purpose ram addresses 0x20 through 0x2f can be accessed through their bit addresses 0x00 through 0x7f. the benefit of bit addressing is that the individual bits can be accessed quickly, without the need for bit masking, which takes more code memory and execution time. the bit addresses for general purpose ram addresses 0x20 through 0x2f can be seen in figure 58. 0x20 07 06 05 04 03 02 01 00 0f 0e 0d 0c 0b 0a 09 08 17 16 15 14 13 12 11 10 1f 1e 1d 1c 1b 1a 19 18 27 26 25 24 23 22 21 20 2f 2e 2d 2c 2b 2a 29 28 37 36 35 34 33 32 31 30 3f 3e 3d 3c 3b 3a 39 38 47 46 45 44 43 42 41 40 4f 4e 4d 4c 4b 4a 49 48 57 56 55 54 53 52 51 50 5f 5e 5d 5c 5b 5a 59 58 67 66 65 64 63 62 61 60 6f 6e 6d 6c 6b 6a 69 68 77 76 75 74 73 72 71 70 7f 7e 7d 7c 7b 7a 79 78 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f byte a dd r ess bit a dd r esses (he x a) figure 58: bit addressable area of general purpose ram bit addressing can be used for instructions that involve boolean variable manipulation and program branchingsee the instruction set. special function registers: special function registers are registers that affect the function of the 8051 core or its peripherals. these registers are located in ram with addresses 0x80 through 0xff. they are only accessible through direct addressing as shown in figure 57 . the individual bits of some of the sfrs can be accessed for use in boolean and program branching instructions. these sfrs are labeled as bit-addressable and the bit addresses are given in the sfr mapping. extended internal ram (xram): the ade7169f16 provides 256 bytes of extended on-chip ram. no external ram is supported. this ram is located in addresses 0x0000 through 0x00ff in the extended ram space. to select the extended ram memory space, the extended indirect addressing modes are used. the internal xram is enabled in the configuration sfr (cfg, 0xaf) by writing 01 to cfg[1:0]. 256 bytes of extended internal ram (xram) 00h ffh figure 59: extended internal ram (xram) space code memory: code and data memory are stored in the 16kbyte flash memory space. no external code memory is supported. to access code memory, code indirect addressing is used. addressing modes the 8052 core provides several addressing modes. the addressing mode determines how the core will interpret the memory location or data value specified in assembly language code. there are six addressing modes as shown in table 59: table 59. 8052 addressing modes addressing mode example bytes core clock cycles immediate mov a, #a8h mov dptr,#a8h 2 3 2 3 direct mov a, a8h mov a, ie mov a, r0 2 2 1 2 2 1 indirect mov a,@r0 1 2 extended direct movx a, @dptr 1 4 extended indirect movx a, @r0 1 4 code indirect movc a, @a+dptr movc a, @a+pc jmp @a+dptr 1 1 1 4 4 3 immediate addressing: in immediate addressing, the expression entered after the number sign (#) will be evaluated by the assembler and stored in the memory address specified.
ade7169f16 preliminary technical data rev. prd | page 76 of 140 this number is referred to as a literal because it refers only to a value and not to a memory location. instructions using this addressing mode will be slower than those between two registers since the literal must be stored and fetched from memory. the expression can be entered as a symbolic variable or an arithmetic expression; the value will be computed by the assembler. direct addressing: with direct addressing, the value at the source address is moved to the destination address. direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers using direct addressing. note that indirect or direct addressing modes can be used to access general purpose ram addresses 0x00 through 0x7f. an instruction with direct addressing that uses an address between 0x80 and 0xff is referring to a special function memory location. indirect addressing: with indirect addressing, the value pointed to by the register is moved to the destination address. for example, to move the contents of internal ram address 82h to the accumulator: mov r0,#82h mov a,@r0 the two instructions above require a total of four clock cycles and three bytes of storage in the program memory. indirect addressing allows addresses to be computed, and is useful for indexing into data arrays stored in ram. note that an instruction that refers to addresses 00 through 7fh is referring to internal ram and indirect or direct addressing modes can be used. an instruction with indirect addressing that uses an address between 80h and ffh is referring to internal ram, not to a sfr. extended direct addressing: the dptr register is used to access internal extended ram in extended indirect addressing mode. the ade7169f16 provides 256 bytes of internal extended ram (xram), accessed through movx instructions. external memory spaces are not supported on this device. in extended direct addressing mode, the dptr register points to the address of the byte of extended ram. the following code will move the contents of extended ram address 100h to the accumulator: mov dptr,#100h movx a,@dptr the two instructions above require a total of seven clock cycles and four bytes of storage in the program memory. extended indirect addressing: the internal extended ram is accessed through a pointer to the address in indirect addressing mode. the ade7169f16 provides 256 bytes of internal extended ram, accessed through movx instructions. external memory is not supported on this device. in extended indirect addressing mode, a register holds the address of the byte of extended ram. the following code will move the contents of extended ram address 80h to the accumulator: mov r0,#80h movx a,@r0 the two instructions above require six clock cycles and three bytes of storage. note that there are 256 bytes of extended ram, so both extended direct and extended indirect addressing can cover the whole address range. there is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the dptr register that is not needed is not stored. from the three examples demonstrating the access of internal ram from 80h through ffh and extended internal ram from 00h through ffh, it can be seen that it is most efficient to use the entire internal ram accessible through indirect access before moving to extended ram. code indirect addressing: the internal code memory can be accessed indirectly. this can be useful for implementing lookup tables and other arrays of constants that are stored in flash. for example, to move the data stored in flash memory at address 8002h into the accumulator: mov dptr,#8002h clr a movx a,@a+dptr the accumulator can be used as a variable index into the array of flash memory located at dptr. instruction set table 60 documents the number of clock cycles required for eachinstruction. most instructions are executed in one or two clock cycles,resulting in a 4 mips peak performance. table 60. instruction set mnemonic description bytes cycles arithmetic add a,rn add register to a 1 1 add a,@ri add indirect memory to a 1 2
preliminary technical data ade7169f16 rev. prd | page 77 of 140 mnemonic description bytes cycles add a,dir add direct byte to a 2 2 add a,#data add immediate to a 2 2 addc a,rn 1 1 add register to a with carry 1 1 addc a,@ri add indirect memory to a with carry 1 2 addc a,dir add direct byte to a with carry 2 2 add a,#data add immediate to a with carry 2 2 subb a,rn subtract register from a with borrow 1 1 subb a,@ri subtract indirect memory from a with borrow 1 2 subb a,dir subtract direct from a with borrow 2 2 subb a,#data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc @ ri increment indirect memory 1 2 inc dir increment direct byte 2 2 inc dptr increment data pointer 1 3 dec a decrement a 1 1 dec rn decrement register 1 1 dec @ri decrement indirect memory 1 2 dec dir decrement direct byte 2 2 mul ab multiply a by b 1 9 div ab divide a by b 1 9 da a a decimal adjust a 1 2 logic anl a,rn and register to a 1 1 anl a,@ri and indirect memory to a 1 2 anl a,dir and direct byte to a 2 2 anl a,#data and immediate to a 2 2 anl dir,a and a to direct byte 2 2 anl dir,#data and immediate data to direct byte 3 3 orl a,rn or register to a 1 1 orl a,@ri or indirect memory to a 1 2 orl a,dir or direct byte to a 2 2 orl a,#data or immediate to a 2 2 orl dir,a or a to direct byte 2 2 orl dir,#data or immediate data to direct byte 3 3 xrl a,rn exclusive-or register to a 1 1 xrl a,@ri exclusive-or indirect memory to a 2 2 xrl a,#data exclusive-or immediate to a 2 2 xrl dir,a exclusive-or a to direct byte 2 2 xrl a, dir exclusive-or indirect memory to a 2 2 xrl dir,#data exclusive-or immediate data to direct 3 3 clr a clear a 1 1 cpl a complement a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1
ade7169f16 preliminary technical data rev. prd | page 78 of 140 mnemonic description bytes cycles data transfer mov a,rn move register to a 1 1 mov a,@ri move indirect memory to a 1 2 mov rn,a move a to register 1 1 mov @ri,a move a to indirect memory 1 2 mov a,dir move direct byte to a 2 2 mov a,#data move immediate to a 2 2 mov rn,#data move register to immediate 2 2 mov dir,a move a to direct byte 2 2 mov rn,dir move register to direct byte 2 2 mov dir,rn move direct to register 2 2 mov @ri,#data move immediate to indirect memory 2 2 mov dir,@ri move indirect to direct memory 2 2 mov @ri,dir move direct to indirect memory 2 2 mov dir,dir move direct byte to direct byte 3 3 mov dir,#data move immediat e to direct byte 3 3 mov dptr,#data move immediate to data pointer 3 3 movc a,@a+dptr move code byte relative dptr to a 1 4 movc a,@a+pc move code b yte relative pc to a 1 1 4 movx a,@ri move extern al (a8) data to a 1 4 movx a,@dptr move exte rnal (a16)data to a 1 4 movx @ri,a move a to ex ternal data (a8) 1 4 movx @dptr,a move a to external data (a16) 1 4 push dir push direct byte onto stack 2 2 pop dir pop direct byte from stack 2 2 xch a,rn exchange a and register 1 1 xch a,@ri exchange a and indirect memory 1 2 xchd a,@ri exchange a and indirect memory nibble 1 2 xch a,dir exchange a and direct byte 2 2 boolean clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c,bit and direct bit and carry 2 2 anl c,/bit and direct bit inverse to carry 2 2 orl c,bit or direct bit and carry 2 2 orl c,/bit or direct bit inverse to carry 2 2 mov c,bit move direct bit to carry 2 2 mov bit,c move carry to direct bit 2 2 branching
preliminary technical data ade7169f16 rev. prd | page 79 of 140 mnemonic description bytes cycles jmp @a+dptr jump indirect relative to dptr 1 3 ret return from subroutine 1 4 reti return from interrupt 1 4 acall addr11 absolute jump to subroutine 2 3 ajmp addr11 absolute jump unconditional 2 3 sjmp rel short jump (relative address) 2 3 jc rel jump on carry equal to 1 2 3 jnc rel jump on carry equal to 0 2 3 jz rel jump on accumulator =0 2 3 jnz rel jump on accumulator not equal to 0 2 3 djnz rn,rel decrement register,jnz relative 2 3 ljmp long jump unconditional 3 4 lcall addr16 long jump to subroutine 3 4 jb bit,rel jump on direct bit =1 3 4 jnb bit,rel jump on direct bit =0 3 4 jbc bit,rel jump on direct bit =1 and clear 3 4 cjne a,dir,rel compare a,direct jne relative 3 4 cjne a,#data,rel compare a,immediate jne relative 3 4 cjne rn,#data,rel compare register,immediate jne relative 3 4 cjne @ri,#data,rel compare indirect,immediate jne relative 3 4 djnz dir,rel decrement direct byte,jnz relative 3 4 miscellaneous nop no operation 1 1 read-modify-write instructions some 8051 instructions read the latch while others read the pin. the state of the pin is read for instructions that input a port bit. instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and rewrite it to the latch. since these instructions involve modifying the port, it is assumed that the pins being modified are outputs, so the output state of the pin is read from the latch. this prevents a possible misinterpretation of the voltage level of a pin. for example, if a port pin is used to drive the base of a transistor, a 1 is written to the bit, to turn the transistor on. if the cpu reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as logic 0. reading the latch rather than the pin returns the correct value of 1. the instructions that read the latch rather than the pins are called read-modify-write instructions, and are listed in table 61. when the destination operand is a port or a port bit, these instructions read the latch rather than the pin. table 61. read-modify-write instructions instruction example description anl anl p0, a logical and orl orl p1, a logical or xrl xrl p2, a logical ex-or jbc jbc p1.1, label jump if bit = 1 and clear bit cpl cpl p2.0 complement bit inc inc p2 increment dec dec p2 decrement djnz djnz p0, label decrement and jump if not zero mov px.y, c 1 mov p0.0,c move carry to bit y of port x clr px.y 1 clr p0.0 clear bit y of port x setb px.y 1 setb p0.0 set bit y of port x ___________________________________________ 1 these instructions read the port byte (all 8 bits), modify the addressed bit, and write the new byte back to the latch. instructions that affect flags many instructions explicitly modify the carry bit such as the mov c, bit and clr c instructions. other instructions that affect status flags are listed in this section.
ade7169f16 preliminary technical data rev. prd | page 80 of 140 add a, source function: adds the source to the accumulator. status flags referenced by instruction: none status flags affected: status flag description c set if there is a carry out of bit 7. cleared otherwise. used to indicate an overflow if the operands are unsigned. ov set if there is a carry out of bit 6 or a carry out of bit 7 but not if both are set. used to indicate an overflow for signed addition. this flag will be set if two positive operands yield a negative result or two negative operands yield a positive result. ac set if there is a carry out of bit 3. cleared otherwise. addc a, source function: adds the source and the carry bit to the accumulator status flags referenced by instruction: carry status flags affected: status flag description c set if there is a carry out of bit 7. cleared otherwise. used to indicate an overflow if the operands are unsigned. ov set if there is a carry out of bit 6 or a carry out of bit 7 but not if both are set. used to indicate an overflow for signed addition. this flag will be set if two positive operands yield a negative result or two negative operands yield a positive result. ac set if there is a carry out of bit 3. cleared otherwise. subb a, source function: subtract the source byte and the carry (borrow) flag from the accumulator. status flags referenced by instruction: carry (borrow) status flags affected: status flag description c set if there is a borrow needed for of bit 7. cleared otherwise. used to indicate an overflow if the operands are unsigned. ov set if there is a borrow is needed for bit 6 or bit 7 but not for both. used to indicate an overflow for signed subtraction. this flag will be set if a negative number subtracted from a positive yields a negative result or it a positive number subtracted from a negative number yields a positive result. ac set if a borrow is needed for bit 3. cleared otherwise. mul ab function: multiplies the accumulator by the b register. this operation is unsigned. the lower byte of the 16-bit product is stored in the accumulator and the higher byte is left in the b register. status flags referenced by instruction: none status flags affected: none status flag description c cleared ov set if the result is greater than 255. cleared otherwise. div ab function: divides the accumulator by the b register. this operation is unsigned. the integer part of the quotient is stored in the accumulator and the remainder goes into the b register. status flags referenced by instruction: none status flags affected: status flag description c cleared ov cleared unless the b register was equal to 0, in which case the results of the division are undefined and the ov flag is set. da a function: adjusts the accumulator to hold two four bit digits after the addition of two binary coded decimals (bcds) with the add or addc instructions. if the ac bit is set or if the value of bits 0-3 exceed 9, 0x06 is added to the accumulator to correct the lower four bits. if the carry bit was set when the instruction began, or if 0x06 was added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits.
preliminary technical data ade7169f16 rev. prd | page 81 of 140 status flags referenced by instruction: carry, ac status flags affected: status flag description c set if the result is greater than 99h. cleared otherwise. rrc a function: rotates the accumulator to the right through the carry flag. the old lsb of the accumulator becomes the new carry flag and the old carry flag is loaded into the new msb of the accumulator. status flags referenced by instruction: carry status flags affected: status flag description c equal to the state of acc.0 before execution of the instruction rlc a function: rotates the accumulator to the left through the carry flag. the old msb of the accumulator becomes the new carry flag and the old carry flag is loaded into the new lsb of the accumulator. status flags referenced by instruction: carry status flags affected: status flag description c equal to the state of acc.7 before execution of the instruction cjne destination, source, relative jump function: compares the value of the source to the value of the destination and branches to the location set by the relative jump if they are not equal. if the values are equal, program execution continues with the instruction after the cjne instruction. status flags referenced by instruction: none status flags affected: status flag description c set if the source value is greater than the destination value. cleared otherwise.
ade7169f16 preliminary technical data rev. prd | page 82 of 140 interrupt system the unique power management architecture of the ade7169f16 includes an operating mode where the 8052 mcu core is shut down, psm2. there are events that can be configured to wake the 8052 mcu core from the psm2 operating mode where the mcu core is shut down. a distinction is drawn here between events that can trigger the wakeup of the 8052 mcu core and events that can trigger an interrupt when the mcu core is active. events that can wake the core are referred to as wakeup events while events that can interrupt the program flow when the mcu is active are called interrupts . see the 3.3v peripherals and wakeup events section to learn more about events that can wake the 8052 core from psm2. the ade7169f16 provides 12 interrupt sources with three priority levels. the power management interrupt is alone at the highest priority level. the other two priority levels are configurable through the interrupt priority sfr (ip, 0xb8) and interrupt enable and priority 2 sfr (ieip2, 0xa9). standard 8051 interrupt architecture the 8051 standard interrupt architecture includes two tiers of interrupts, where some interrupts are assigned a high priority and others are assigned a low priority. priority 0 priority 1 high low figure 60: standard 8051 interrupt priority levels a priority 1 interrupt can interrupt the service routine of a priority 0 interrupt, and if two interrupts of different priorities occur at the same time, the priority 1 interrupt is serviced first. an interrupt cannot be interrupted by another interrupt of the same priority level. if two interrupts of the same priority level occur simultaneously, a polling sequence is observed. see the interrupt priority section. ade7169f16 interrupt architecture the ade7169f16 provides advanced power supply monitoring features. to ensure a fast response to time critical power supply issues, such as a loss of line power, the power supply monitoring interrupt should be able to interrupt any interrupt service routine. in order to enable the user to make full use of the standard 8051 interrupt priority levels, an additional priority level was added for the power supply management, psm, interrupt. the psm interrupt is the only interrupt at this highest interrupt priority level. priority 0 priority 1 psm high low figure 61: ade7169f16 interrupt architecture see the power supply monitor interrupt (psm) section for more information on the psm interrupt. interrupt sfr register list the control and configuration of the interrupt system is carried out through three interrupt-related sfrs: sfr address default va lu e bit addressable description ie 0xa8 0x00 yes interrupt enable register ip 0xb8 0x00 yes interrupt priority register ieip2 0xa9 0xa0 no secondary interrupt enable register wdcon 0xc0 0x10 yes watchdog timer configuration table 62. interrupt enable sfr (ie, 0xa8) bit location bit addr. bit name description 7 0xaf ea set by the user to en able all interrupt sources. cleared by the user to disa ble all interrupt sources. 6 0xae etemp set by the user to en able the temperature adc interrupt. 5 0xad et2 set by the user to enable the timer 2 interrupt. 4 0xac es set by the user to enable the uart serial port interrupt. 3 0xab et1 set by the user to enable the timer 1 interrupt. 2 0xaa ex1 set by the user to enable external interrupt 1 (int1 ). 1 0xa9 et0 set by the user to enable the timer 0 interrupt.
preliminary technical data ade7169f16 rev. prd | page 83 of 140 0 0xa8 ex0 set by the user to enable external interrupt 0 ( ). table 63. interrupt priority sfr (ip, 0xb8) bit location bit addr. bit name description 7 0xbf pade ade energy measurement interrupt priority (1 = high; 0 = low). 6 0xbe ptemp temperature adc interrupt priority (1 = high; 0 = low). 5 0xbd pt2 timer 2 interrupt priority (1 = high; 0 = low). 4 0xbc ps uart serial port interrupt priority (1 = high; 0 = low). 3 0xbb pt1 timer 1 interrupt priority (1 = high; 0 = low). 2 0xba px1 int1 (external interrupt 1) priority (1 = high; 0 = low). 1 0xb9 pt0 timer 0 interrupt priority (1 = high; 0 = low). 0 0xb8 px0 int0 (external interrupt 0) priority (1 = high; 0 = low). table 64. interrupt enable and priority 2 sfr (ieip2, 0xa9) bit location bit mnemonic description 7 6 pti rtc interrupt priority (1 = high; 0 = low). 5 4 psi spi/i2c interrupt priority (1 = high; 0 = low). 3 eade set by the user to enable th e energy metering interrupt (ade) 2 eti set by the user to enable the rtc interval timer interrupt. 1 epsm set by the user to enable the psm power supply management interrupt. 0 esi set by the user to enable the spi/i2c interrupt. table 65. watchdog timer sfr (wdcon, 0xc0) bit location bit addr. bit name default value description 7-4 0xc7 C 0xc4 pre[3:0] 7 watchdog pre-scaler. in normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768khz). the pre bits set wh ich of the upper bits of the counter are used as the watchdog output following: clki n t pre watchdog 9 2 2 = [3:0] watchdog timeout 0000 15.6ms 0001 31.2ms 0010 62.5ms 0011 125ms 0100 250ms 0101 500ms 0110 1s 0111 2s 1000 0 automatic reset 1001 0 serial download reset 1010 to 1111 not a valid selection 3 0xc3 wdir 0 watchdog interrupt response bit. when clear, watchdog will generate a system reset when the watchdog time out period has expired when set, the watchdog will generate a interrupt when the watchdog time out period has expired.
ade7169f16 preliminary technical data rev. prd | page 84 of 140 2 0xc2 wds 0 wds watchdog status bit. this bit is set to indicate that a watchdog timeout has occurred. wds is cleared by writing a zero or by an external hardware reset. a watchdog reset will not clear wds. the bit can theref ore be used to distinguish between a watchdog reset and a hardware reset from the reset pin. 1 0xc1 wde 1 wde watchdog enable bit. when set, enables the watchdog and cl ears its counter (e.g. 2 above). the watchdog counter is subsequently cleare d again whenever the wde bit is set. if the watchdog is not cleared within its selected timeout period it will generate a system reset or watchdog interrupt, depe nding on the wdir bit. the watchdog is disabled (and wde cleared) by any of the following: write zero to wde watchdog reset (wdir = 0) hardware reset psm interrupt lock interrupt. 0 0xc0 wdwr 0 wdwr watchdog write enable bit. to wr ite data into the wdcon sfr involves a double instruction sequence. the wdwr bit must be set and the following instruction must be a write instruction to the wdcon sfr. this sequence is necessary so that the wdcon sfr is pr otected from code execution upsets that might unintentionally modify this sfr. in terrupts should be disabled during this operation due to the consecutive instruction cycles. e.g. disable watch dog 1 write to wdcon e.g. 2 clear wde bit clr ea setb wdwr clr wde setb ea interrupt priority if two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in table 66 , is observed. table 66. priority within interrupt level source priority description ipsm 0 (highest) power supply monitor interrupt irtc 1 rtc interval timer interrupt iade 2 ade energy measurement interrupt wdt 3 watchdog timer overflow interrupt itemp 4 temperature adc interrupt ie0 5 external interrupt 0 tf0 6 timer/counter 0 interrupt ie1 7 external interrupt 1 tf1 8 timer/counter 1 interrupt ispi/i2ci 9 spi/i 2 c interrupt ri/ti 10 uart serial port interrupt tf2/exf2 11 (lowest) t imer/counter 2 interrupt interrupt flags the interrupt and status flags associated with the interrupt vectors are shown in table 67 and table 68. most of the interrupts have flags associated with them.
preliminary technical data ade7169f16 rev. prd | page 85 of 140 table 67. interrupt flags interrupt source flags bit address details ie0 tcon.1 ie0 external interrupt 0 tf0 tcon.5 tf0 timer 0 ie1 tcon.3 ie1 external interrupt 1 tf1 tcon.7 tf1 timer 1 scon.1 ti transmit interrupt ri + ti scon.0 ri receive interrupt t2con.7 tf2 timer 2 overflow flag tf2 + exf2 t2con.6 exf2 timer 2 external flag itemp (temperature adc) - the temperature adc interrupt does not ha ve an interrupt flag associated with it. ipsm (power supply) ipsmf.6 fpsm psm interrupt flag iade (energy measurement dsp) mirqstl.7 read mirqsth, mirqstm, mirqstl. if the au toclr bit in the ipsme sfr is set, each of these bytes will be reset after they are read. this is done on a per byte basis. reading mirqsth reads and clears only mirqsth. table 68. status flags interrupt source flags bit address details itemp (temperature adc) - the temperature adc interrupt does not have an status flag associated with it. spi2cstat spi interrupt status register ispi/i2ci spi2cstat i 2 c interrupt status register timecon.7 rtc midnight flag irtc (rtc interval timer) timecon.2 rtc alarm flag wdt (watchdog timer) wdcon.2 wds watchdog timeout flag a functional block diagram of the interrupt system is shown in figure 62. note that the psm interrupt is the only interrupt in the highest priority level. if an external wakeup event occurs to wake the ade7169f16 from psm2, a pending external interrupt will be generated. when the ex0 or ex1 bits are set in the interrupt enable sfr (ie, 0xa8) to enable external interrupts, the program counter will be loaded with the ie0 or ie1 interrupt vector. the ie0 and ie1 interrupt flags in the tcon register will not be affected by events that occur when the 8052 mcu core is shut down during psm2 see the power supply monitor interrupt (psm) section. the rtc, temperature adc and i2c/spi interrupts are latched such that pending interrupts cannot be cleared without entering their respective interrupt service routines. clearing the rtc midnight and alarm flags will not clear a pending rtc interrupt. similarly, clearing the i2c/spi status bits in the spi interrupt status register sfr (spistat, 0xea) will not cancel a pending i2c/spi interrupt. these interrupts will remain pending until the rtc or i2c/spi interrupt vectors are enabled. their respective interrupt service routines will be entered shortly thereafter. figure 62 shows how the interrupts are cleared when the interrupt service routines are entered. some interrupts with multiple interrupt sources are not automatically cleared, specifically the psm, ade, uart and timer 2 interrupt vectors. note that the int0 and int1 interrupts are only cleared if the external interrupt is configured to be triggered by a falling edge, by setting it0 in the timer/counter 0 and 1 control sfr (tcon, 0x88). if int0 or int1 is configured to interrupt on a low level, the interrupt service routine will be reentered until the respective pin goes high.
ade7169f16 preliminary technical data rev. prd | page 86 of 140 ipsmf fpsm (ipsmf.6) ipsme individual interrupt enables global interrupt enable (ea) ie/ieip2 registers ip/ieip2 registers watchdog timeout wdir low high highest midnight alarm in out latch reset mirqsth mirqstm mirqstl mirqenh mirqenm mirqenl mirqstl.7 tempadc interrupt in out latch reset int0 it0 0 1 ie0 tf0 int1 it1 0 1 tf1 in out latch reset cfg.5 0 1 i2c interrupt spi interrupt ri ti tf2 exf2 priority level interrupt polling sequence psm rtc ade watchdog temp adc external interrupt 0 timer 0 external interrupt 1 timer 1 i2c/spi uart timer 2 automatic clear signal legend it0 ie1 it1 psm2 psm2
preliminary technical data ade7169f16 rev. prd | page 87 of 140 figure 62: interrupt system functional block diagram interrupt vectors when an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. when the interrupt service routine has been completed, the program counter is popped off the stack by a reti instruction. this allows program execution to resume from where it was interrupted. the interrupt vector addresses are shown in table 69. table 69. interrupt vector addresses source vector address ie0 0x0003 tf0 0x000b ie1 0x0013 tf1 0x001b ri + ti 0x0023 tf2 + exf2 0x002b itemp (temperature adc) 0x0033 ispi/i2ci 0x003b ipsm (power supply) 0x0043 iade (energy measurement dsp) 0x004b irtc (rtc interval timer) 0x0053 wdt (watchdog timer) 0x005b watch dog functionality the watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ade7169f16 enters an erroneous state, possibly due to a programming error or electrical noise. the watchdog is enabled by default with a time out of 2 seconds and will create a system reset if not cleared within 2 seconds. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (watchdog timer sfr (wdcon, 0xc0). when enabled, the watchdog circuit generates a system reset or interrupt (wds) if the user program fails to set the wde bit within a predetermined amount of time (see the pre30 bits in table 65). the watchdog timer is clocked from the 32 khz external crystal connected between the clkin and clkout pins. the wdcon sfr can be written only by user software if the double write sequence described in wdwr is initiated on every write access to the wdcon sfr watchdog timer interrupt if the watchdog timer is not cleared within the watchdog timeout period, a system reset will occur unless the watchdog timer interrupt is enabled. the watchdog timer interrupt enable bit is located in the watchdog timer sfr (wdcon, 0xc0). enabling the watchdog timer interrupt allows the program to examine the stack or other variables that could have led the program astray. the watchdog timer interrupt also allows the watchdog to be used as a long interval timer. note that the watchdog timer interrupt is automatically configured as a high priority interrupt. this interrupt cannot be disabled by the ea bit in the ie register. even if all of the other interrupts are disabled, the watchdog is kept active to watch over the program. interrupt latency the 8051 architecture requires that at least one instruction executes between interrupts. to ensure this, the 8051 mcu core hardware prevents the program counter from jumping to an isr immediately after completing a reti instruction or an access of the ip and ie registers. the shortest interrupt latency is 3.25 instruction cycles, 800ns with a clock of 4.096mhz. the longest interrupt latency for a high priority interrupt results when a pending interrupt is generated during a low priority interrupt reti, followed by a multiply instruction. this results in a maximum interrupt latency of 16.25 instruction cycles, 4us with a clock of 4.096mhz. context saving when the 8052 vectors to an interrupt, only the program counter is saved on the stack. therefore the interrupt service routine must be written to ensure that registers that are used in the main program are restored to their pre-interrupt state. common registers that may be modified in the isr are the accumulator, and the psw register. any general purpose registers that are used as scratchpads in the isr should also be restored before exiting the interrupt. the example 8051 code shown below shows how to restore some commonly used registers: generalisr: ; save the current accumulator value push acc ; save the current status and register bank selection push psw ; service interrupt ; restore the status and register bank selection pop psw ; restore the accumulator pop acc reti
preliminary technical data ade7169f16 rev. prd | page 88 of 140 lcd driver the lcd module is capable of directly driving an lcd panel of 24 x 4 segments without compromising any ade7169f16 functionalities. using shared pins, the driver can accommodate an lcd with up to 26 x 4 segments. it is capable of driving lcds with 2x, 3x and 4x multiplexing. lcd waveform voltages generated through internal charge pump circuitry support up to 5v lcds. an external resistor ladder for lcd waveform voltage generation is also supported. the ade7169f16 has an embedded lcd control circuit, lcd driver and power supply circuit. the lcd module is functional in all operating modes. lcd sfr register list there are six lcd control registers that configure the driver for the specific type of lcd in the end system and set up the user display preferences. the lcd configuration sfr (lcdcon, 0x95), lcd configuration x sfr (lcdconx, 0x9c) and lcd configuration y sfr (lcdcony, 0xb1) sfrs contains general lcd driver configuration information including the lcd enable and reset, as well as method of lcd voltage generation and the multiplex level. the lcd clock sfr (lcdclk, 0x96) configures timing settings for lcd frame rate and blink rate. lcd pins are configured for lcd functionality in the lcd segment enable sfr (lcdsege, 0x97) and lcd segment enable 2 sfr (lcdsege2, 0xed). table 70. lcd driver sfrs sfr address (hex) r/w name description 0x95 r/w lcdcon lcd configuration sfr 0x96 r/w lcdclk lcd clock 0x97 r/w lcdsege lcd segment enable 0x9c r/w lcdconx lcd configuration x 0xac r/w lcdptr lcd pointer 0xae r/w lcddat lcd data 0xb1 r/w lcdcony lcd configuration y 0xed r/w lcdsege2 lcd segment enable 2 table 71. lcd configuration sfr (lcdcon, 0x95) bit location bit mnemonic default value description 7 lcden 0 lcd enable. if this bit is set, the lcd driver is enabled. 6 lcdrst 0 lcd data registers are reset to zero. if this bit is set, the lcd data registers will be reset to zero. 5 blinken 0 blink mode enable bit. if this bit is set, blink mode is enable d. the blink mode is configured by the blkmod[1:0] and blkfreq[1:0] bits in the lcd clock sfr (lcdclk, 0x96) force lcd off when in psm2 (sleep mode). 0 the lcd is disabled or enabled in psm2 by lcden bit. 4 lcdpsm2 0 1 the lcd is disabled in psm2 regarless of lcden setting. lcd clock selection f lcdclk 0 2048hz 3 clksel 0 1 128hz bias mode 0 1/2 2 bias 0 1 1/3 1-0 lmux[1:0] 0 lcd multiplex level
preliminary technical data ade7169f16 rev. prd | page 89 of 140 lmux[1:0] 0 0 reserved 0 1 2x fp27/com3 is used as fp27 fp28/com2 is used as fp28 1 0 3x fp27/com3 is used as fp27 fp28/com2 is used as com2 1 1 4x fp27/com3 is used as com3 fp28/com2 is used as com2 table 72. lcd configuration x sfr (lcdconx, 0x9c) bit location bit mnemonic default value description 7 reserved 0 reserved external resistor ladder selection bit. 0 external resistor ladder is disabled. charge pump is enabled. 6 extres 0 1 external resistor ladder is enab led. charge pump is disabled. 5-0 biaslvl[5:0] 0 bias level selection bits. see table 73. table 73. lcd bias voltage when contrast control is enabled 1/2 bias 1/3 bias blvl[5] v a (v) v b v c v b v c 0 [] 31 0 : 4 blvl v ref 1 [] ? ? ? ? ? ? + 31 0 : 4 1 blvl v ref v b = v a v c = 2 x v a v b = 2 x v a v c = 3 x v a table 74. lcd configuration y sfr (lcdcony, 0xb1) bit location bit mnemonic default value description 7 reserved 0 this bit should be kept cleared for proper operation 6 inv_lvl 0 frame inversion mode enable bit if this bit is set, frames are inverted every other frame if this bit is cleared, frames are not inverted 5-2 reserved 0 these bits should be kept cleared for proper operation 1 updateover 0 update finished flag bi t. this bit is updated by lcd driver. when set, indicates that the lcd memory has been updated and a new frame has begun. 0 refresh 0 refresh lcd data memory bi t, this bit should be set by user. when set, the lcd driver does not use the data in the lcd data registers to update display. the lcd data regist ers can be updated by the 8052. when clear, the lcd driver will use the data in the lcd data registers to update display at the next frame. table 75. lcd clock sfr (lcdclk, 0x96) bit location bit mnemonic default value description
ade7169f16 preliminary technical data rev. prd | page 90 of 140 blink mode clock source configuration bits blkmod[1:0] 0 0 the blink rate is controlled by software. the display is off. 0 1 the blink rate is controlled by software. the display is on. 1 0 the blink rate is 2 hz 7-6 blkmod[1:0] 0 1 1 the blink rate is set by blkfreq[1:0] blink rate configuration bits these bits control lcd blink rate if blkmod[1:0]=11 blkfreq[1: 0] blink rate (hz) 0 0 1 0 1 1/2 1 0 1/3 5-4 blkfreq[1:0] 0 1 1 1/4 3-0 fd[3:0] 0 lcd frame rate select ion bits. see table 76 and table 77. table 76. lcd frame rate selection for f lcdclk =2048hz (lcdcon[3]=0) 2x multiplexing 3x multiplexing 4x multiplexing fd3 fd2 fd1 fd0 f lcd (hz) frame rate (hz) f lcd (hz) frame rate (hz) f lcd (hz) frame rate (hz) 0 0 0 1 256 128 512 170.7 512 128 0 0 1 0 170.7 85.3 341.3 113.8 341.3 85.3 0 0 1 1 128 64 256 85.3 256 64 0 1 0 0 102.4 51.2 204.8 68.3 204.8 51.2 0 1 0 1 85.3 42.7 170.7 56.9 170.7 42.7 0 1 1 0 73.1 36.6 146.3 48.8 146.3 36.6 0 1 1 1 64 32 128 42.7 128 32 1 0 0 0 56.9 28.5 113.8 37.9 113.8 28.5 1 0 0 1 51.2 25.6 102.4 34.1 102.4 25.6 1 0 1 0 46.5 23.25 93.1 31 93.1 23.25 1 0 1 1 42.7 21.35 85.3 28.4 85.3 21.35 1 1 0 0 39.4 19.7 78.8 26.3 78.8 19.7 1 1 0 1 36.6 18.3 73.1 24.4 73.1 18.3 1 1 1 0 34.1 17.05 68.3 22.8 68.3 17.05 1 1 1 1 32 16 64 21.3 64 16 0 0 0 0 16 8 32 10.7 32 8 table 77. lcd frame rate selection for f lcdclk =128hz (lcdcon[3]=1) 2x multiplexing 3x multiplexing 4x multiplexing fd3 fd2 fd1 fd0 f lcd (hz) frame rate (hz) frame rate (hz) frame rate (hz)
preliminary technical data ade7169f16 rev. prd | page 91 of 140 1 1 1 1 128 64 42.7 32 0 0 0 0 64 32 21.3 16 0 0 0 1 32 16 10.7 8 0 0 1 0 21.3 10.6 10.7 8 0 0 1 1 16 8 10.7 8 : boxes shaded in grey are not within the range of typical lcd frame rates table 78. lcd segment enable sfr (lcdsege, 0x97) bit location bit mnemonic default value description fp25 function select bit 0 general purpose i/o 7 fp25en 0 1 lcd function fp24 function select bit 0 general purpose i/o 6 fp24en 0 1 lcd function fp23 function select bit 0 general purpose i/o 5 fp23en 0 1 lcd function fp22 function select bit 0 general purpose i/o 4 fp22en 0 1 lcd function fp21 function select bit 0 general purpose i/o 3 fp21en 0 1 lcd function fp20 function select bit 0 general purpose i/o 2 fp20en 0 1 lcd function delay before powerdown? fdelay[1:0] 0 0 no timeout 0 1 2 cycles 1 0 4 cycles 1-0 fdelay 0 1 1 8 cycles table 79. lcd pointer sfr (lcdptr, 0xac) bit location bit mnemonic default value description 7 w/r 0 read or write lcd bit if this bit is set, the data in lc ddat will be written to the address indicated by the bits lcdptr[5 :0] 6 reserved 0 reserved 5-0 address 0 lcd memory address - see table 82.
ade7169f16 preliminary technical data rev. prd | page 92 of 140 table 80. lcd data sfr (lcddat, 0xae) bit location bit mnemonic default value description 7-0 lcddata 0 data to be written into or read out of the lcd memory sfrs. table 81. lcd segment enable 2 sfr (lcdsege2, 0xed) bit location bit mnemonic default value description 7-4 reserved 0 reserved fp19 function select bit 0 general purpose i/o 3 fp19en 0 1 lcd function fp18 function select bit 0 general purpose i/o 2 fp18en 0 1 lcd function fp17 function select bit 0 general purpose i/o 1 fp17en 0 1 lcd function fp16 function select bit 0 general purpose i/o 0 fp16en 0 1 lcd function lcd setup the lcd configuration sfr (lcdcon, 0x95) configures the lcd module to drive the type of lcd in the user end system. the bias and lmux[1:0] bits in this sfr should be set according to the lcd specifications. the com2/fp28 and com3/fp27 pins default to lcd segment lines. selecting the 3x multiplex level in the lcd configuration sfr (lcdcon, 0x95) by setting lmux[1:0] to 2d, changes the fp28 pin functionality to com2. the 4x multiplex level selection, lmux[1:0]=3d, changes the fp28 pin to com2 and the fp27 pin to com3. lcd segments fp0-fp15 are enabled by default. additional pins are selected for lcd functionality in the lcd segment enable sfr (lcdsege, 0x97) and lcd segment enable 2 sfr (lcdsege2, 0xed) where there are individual enable bits for segment pins fp16-25. the lcd pins do not have to be enabled sequentially. for example, if the alternate function of fp23, the timer 2 input, is required, then any of the other shared pins, fp16-25, could be enabled instead. the display element control section contains details about setting up the lcd data memory to turn individual lcd segments on and off. setting the lcdrst bit in the lcd configuration sfr (lcdcon, 0x95) will reset the lcd data memory to its default, zero. a power on reset also clears the lcd data memory. lcd timing and waveforms an lcd segment acts like a capacitor that is charged and discharged at a certain rate. the rate at which these capacitors are charged and discharged, the refresh rate, determines the visual characteristics of the lcd. a slow refresh rate will result in the user being able to see the lcd blink on and off in between refreshes. a fast refresh rate will present a screen that appears to be lit up continuously. however, a faster refresh rate consumes more power. the frame rate, or refresh rate, for the lcd module is derived from the lcd clock, f lcdclk . the lcd clock is selected as 2048hz or 128hz by the clksel bit in the lcd configuration x sfr (lcdconx, 0x9c). the minimum refresh rate that is needed for the lcd to appear solid, without blinking, is independent of the multiplex level. the lcd waveform frequency, f lcd , is the frequency at which the lcd switches which common line is active. thus the lcd waveform frequency depends heavily on the multiplex level. the frame rate and lcd waveform frequency are set by f lcdclk , the multiplex level and the fd[3:0] frame rate selection bits in the lcd clock sfr (lcdclk, 0x96). the lcd module provides 16 different frame rates for f lcdclk =2048hz, ranging from 8 to 128hz for an lcd with 4x multiplexing. there are fewer options available with f lcdclk =128hz, ranging from 8 to 32hz for a 4x multiplexed
preliminary technical data ade7169f16 rev. prd | page 93 of 140 lcd. the 128hz clock is beneficial for battery operation because it consumes less power than the 2048hz clock. the frame rate is set by the fd[3:0] bits in the lcd clock sfr (lcdclk, 0x96)see table 76 and table 77. the lcd waveform is inverted at twice the lcd waveform frequency, f lcd . this way each frame has an average dc offset of zero. adc offset would degrade the lifetime and performance of the lcd. blink mode blink mode is enabled by setting the blinken bit in the lcd configuration sfr (lcdcon, 0x95). this mode is used to alternate between lcd on and off states so that the lcd screen appears to blink. there are two blinking modes: a software controlled blink mode and an automatic blink mode. software controlled blink mode the lcd blink rate can be controlled by user code with the blkmod[1:0] bits in the lcd clock sfr (lcdclk, 0x96) by toggling the bits to turn the display on and off at a rate determined by the mcu code. automatic blink mode there are five blink rates available if the rtc peripheral is enabled (enable the rtc byxxx). these blink rates are selected by the blkmod[1:0] and blkfreq[1:0] bits in the lcd clock sfr (lcdclk, 0x96) C see table 75. display element control a bank of 15 bytes of data memory located in the lcd module controls the on or off state of each segment of the lcd. the lcd data memory is stored in addresses 0 through 14 in the lcd module. each byte configures the on and off states of two segment lines. the lsbs store the state of the even numbered segment lines and the msbs store the state of the odd numbered segment lines. for example, lcd data address zero refers to segment lines one and zerosee table 82. note that the lcd data memory is maintained in the psm2 operating mode. table 82. lcd data memory accessed indirectly through lcd pointer sfr (lcdptr, 0xac) and lcd data sfr (lcddat, 0xae) lcd memory address com3 com2 com1 com0 com3 com2 com1 com0 0eh fp28 fp28 fp28 fp28 0dh fp27 fp27 fp27 fp27 fp26 fp26 fp26 fp26 0ch fp25 fp25 fp25 fp25 fp24 fp24 fp24 fp24 0bh fp23 fp23 fp23 fp23 fp22 fp22 fp22 fp22 0ah fp21 fp21 fp21 fp21 fp20 fp20 fp20 fp20 09h fp19 fp19 fp19 fp19 fp18 fp18 fp18 fp18 08h fp17 fp17 fp17 fp17 fp16 fp16 fp16 fp16 07h fp15 fp15 fp15 fp15 fp14 fp14 fp14 fp14 06h fp13 fp13 fp13 fp13 fp12 fp12 fp12 fp12 05h fp11 fp11 fp11 fp11 fp10 fp10 fp10 fp10 04h fp9 fp9 fp9 fp9 fp8 fp8 fp8 fp8 03h fp7 fp7 fp7 fp7 fp6 fp6 fp6 fp6 02h fp5 fp5 fp5 fp5 fp4 fp4 fp4 fp4 01h fp3 fp3 fp3 fp3 fp2 fp2 fp2 fp2 00h fp1 fp1 fp1 fp1 fp0 fp0 fp0 fp0 com# designates the common lines fp# designates the segment lines the lcd data memory is accessed indirectly through the lcd pointer sfr (lcdptr, 0xac)and table 80. lcd data sfr (lcddat, 0xae). moving a value to the lcd pointer sfr (lcdptr, 0xac) selects the lcd data byte to be accessed and initiates a read or write operationsee table 79. writing to lcd data registers to update the lcd data memory, first set the lsb of the lcd configuration y sfr (lcdcony, 0xb1) to freeze the data being displayed on the lcd while updating it. then, move the data to the lcd data sfr (lcddat, 0xae) prior to accessing the lcd pointer sfr (lcdptr, 0xac). when the msb of the lcd pointer sfr (lcdptr, 0xac) is set, the content of the lcd data sfr (lcddat, 0xae) is transferred to the internal lcd data memory designated by the address in the lcd pointer sfr (lcdptr, 0xac). clear the lsb of the lcd configuration y sfr (lcdcony, 0xb1) when all of the data memory has been updated to allow to use the new lcd set up for display. sample 8052 code to update the segments attached to pins fp10 and fp11 on is shown below: orl lcdcony,#01h ; start updating the data mov lcddata,#ffh mov lcdptr,#80h or 05h anl lcdcony,#0feh ; update finished reading lcd data registers when the msb of the lcd pointer sfr (lcdptr, 0xac) is cleared, the content of the lcd data memory address designated by lcdptr are transferred to the lcd data sfr (lcddat, 0xae). sample 8052 code to read the contents of lcd data memory address 07h, which holds the on and off state of the segments attached to fp14 and fp15, is shown below: mov lcdptr,#not 80h and 07h mov r1, lcddata voltage generation the ade7169f16 provides two ways to generate the lcd
ade7169f16 preliminary technical data rev. prd | page 94 of 140 waveform voltage levels. the on-chip charge pump option can generate 5v. this makes it possible to use 5v lcds with the 3.3v ade7169f16. there is also an option to use an external resistor ladder with a 3.3v lcd. the extres bit in the lcd configuration x sfr (lcdconx, 0x9c) selects the resistor ladder or charge pump option. when selecting how to generate the lcd waveform voltages, the following should be considered: ? power consumption ? contrast control ? lifetime performance power consumption in most lcds, a high amount of current is required when the lcd waveforms change state. the external resistor ladder option draws a constant amount of current whereas the charge pump circuitry allows dynamic current consumption. if the lcd module is used with the internal charge pump option, when the display is disabled, the voltage generation is disabled, so that no power is consumed by the lcd function. this feature will result in significant power savings if the display is turned off in battery operation. contrast control the electrical characteristics of the liquid in the lcd change over temperature, requiring adjustments in the lcd waveform voltages to ensure a readable display. an added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the lcd. these compensations can be performed based on the ade7169f16 temperature and supply voltage measurementssee the temperature, battery and supply voltage measurements section. this dynamic contrast control is not easily implemented with external resistor ladder voltage generation. the lcd bias voltage sets the contrast of the display when the charge-pump provides the lcd waveform voltages. the ade7169f16 provides 64 bias levels selectable using the blvl bits in the lcd configuration x sfr (lcdconx, 0x9c). the voltage level on lcdva, lcdvb and lcdvc depend on the the interntal voltage reference value (vref), blvl[5:0] selection and the biasing selected as described in table 73. lifetime performance dc offset on a segment will degrade its performance over time. the voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the lcd. lcd external circuitry the voltage generation selection is made by bit extres in the lcd configuration x sfr (lcdconx, 0x9c). this bit is clear by default for charge pump voltage generation but can be set to enable an external resistor ladder. charge pump: voltage generation through the charge pump requires external capacitors to store charge. the external connections to va, vb, and vc as well as vp1 and vp2 are shown in lcd configuration x sfr (lcdconx, 0x9c). lcdva lcdvb lcdvc lcdvp1 lcdvp2 charge pump and lcd waveform circuitry 470nf 470nf 470nf 100nf figure 63: external circuitry for charge pump option external resistor ladder: to enable the external resistor ladder option, set the extres bit in the lcd configuration x sfr (lcdconx, 0x9c). when extres=1, the lcd waveform voltages are supplied by the external resistor ladder. since the lcd voltages are not being generated on-chip, the lcd bias compensation implemented to maintain contrast over temperature and supply is not possible. the external circuitry needed for the resistor ladder option is shown in figure 64. the resistors required should be in the range of 10k to 100k and based on the current required by the lcd being used. lcdva lcdvb lcdvc lcdvp1 lcdvp2 lcd waveform circuitry figure 64: external circuitry for external resistor ladder option lcd function in psm2 the lcdpsm2 bit in the lcd configuration sfr (lcdcon, 0x95) and the lcden bit in the lcd configuration sfr
preliminary technical data ade7169f16 rev. prd | page 95 of 140 (lcdcon, 0x95) control lcd functionality in the psm2 operating mode. lcdpsm2 lcden comments 0 0 the display is off in psm2. 0 1 the display is on in psm2. 1 x the display is off in psm2. note that the lcd configuration and data memory is retained when the display is turned off. example lcd setup an example to set up the lcd peripheral for a specific lcd is described below. type of lcd: 5v, 4x multiplexed with 1/3 bias, 96 segments voltage generation: internal charge pump refresh rate: 64hz a 96 segment lcd with 4x multiplexing requires 96/4=24 segment lines. there are 16 pins that automatically dedicated for use as lcd segments, fp0 to fp15. eight more pins must be chosen for the lcd function. since the lcd has 4x multiplexing, all four common lines are used so com2/fp28 and com3/fp27 cannot be utilized as segment lines. based on the alternate functions of the pins used for fp16 through fp25, fp16-23 are chosen for the seven remaining segment lines. these pins will be enabled for lcd functionality in the lcd segment enable sfr (lcdsege, 0x97) and lcd segment enable 2 sfr (lcdsege2, 0xed). to determine contrast setting for this 5v lcd, look in table 73 to find the biaslvl[5:0] setting that corresponds to a vc of 5v in 1/3 bias mode. the nominal bias level setting for this lcd is biaslvl[5:0]=[111111]. the lcd is setup with the following 8052 code: ; setup lcd pins to have lcd functionality mov lcdseg, # fp20en+fp21en+fp22en+fp23en mov lcdsegx, #fp16en+fp17en+fp18en+fp19en ; setup lcdcon for f lcdclk =2048hz, 1/3 bias and 4x multiplexing mov lcdcon, #bias+lmux1+lmux0 ; setup lcdconx for charge pump and biaslvl[1110111] mov lcdconx, #biaslvl5+biaslvl4+biaslvl3+ biaslvl2+biaslvl1+biaslvl0 ; set up refresh rate for 64hz with f lcdclk =2048hz, from table 76 mov lcdclk, #fd3+fd2+fd1+fd0 ; set up lcd data registers with data to be displayed using ; lcdptr and lcddata registers ; turn all segments on fp25 on and fp26 off orl lcdcony,#01h ; start data memory refresh mov lcddat, #f0h mov lcdptr, #80h or 0dh anl lcdcony,#0feh ; end of data memory refresh orl lcdcon,#lcden ; enable lcd to setup the same 3.3v lcd for use with an external resistor ladder: ; setup lcd pins to have lcd functionality mov lcdseg, #fp20en+fp21en+fp22en+fp23en mov lcdsegx, #fp16en+fp17en+fp18en+fp19en ; setup lcdcon for f lcdclk =2048hz, 1/3 bias and 4x multiplexing mov lcdcon, #bias+lmux1+lmux0 ; setup lcdconx for external resistor ladder mov lcdconx, #extres ; set up refresh rate for 64hz with f lcdclk =2048hz, from table 76 mov lcdclk, #fd3+fd2+fd1+fd0 ; set up lcd data registers with data to be displayed using ; lcdptr and lcddata registers ; turn all segments on fp25 on and fp26 off orl lcdcony,#01h ; start data memory refresh mov lcddat, #f0h mov lcdptr, #80h or 0dh anl lcdcony,#0feh ; end of data memory refresh orl lcdcon,#lcden ; enable lcd
ade7169f16 preliminary technical data rev. prd | page 96 of 140 flash memory flash memory overview flash memory is a type of non-volatile memory that is in- circuit programmable. the default, erased, state of a byte of flash memory is 0xff. when a byte of flash memory is programmed, the required bits change from one to zero. the flash memory must be erased to turn the zeros back to ones. however, a byte of flash memory cannot be erased individually. the entire segment, or page, of flash memory that contains the byte must be erased. the ade7169f16 provides 16kbytes of flash program/information memory. this memory is segmented into 32 pages of 512 bytes each. so, to reprogram one byte of flash memory, the 511 bytes in that page must be erased. the flash memory can be erased by page or all at once in a mass erase. there is a command to verify that a flash write operation has completed successfully. the ade7169f16 flash memory controller also offers configurable flash memory protection. the 16 kbytes of flash memory are provided on-chip to facilitate code execution without any external discrete rom device requirements. the program memory can be programmed in- circuit, using the serial download mode provided or using conventional third party memory programmers. flash/ee memory reliability the flash memory arrays on the ade7169f16 are fully qualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events: 1. initial page erase sequence 2. read/verify sequence 3. byte program sequence 4. second read/verify sequence in reliability qualification, every byte in both the program and data flash/ee memory is cycled from 00h to ffh until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification table, the ade7169f16 flash memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of C40c, +25c and +85c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with a minimum endurance figure of 20,000 cycles of operation at 25c. retention is the ability of the flash memory to retain its programmed data over time. again, the parts have been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55c). as part of this qualification procedure, the flash memory is cycled to its specified endurance limit described previously, before data retention is characterized. this means that the flash memory is guaranteed to retain its data for its full specified retention lifetime every time the flash memory is reprogrammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, derates with t j as shown in figure 65. 40 60 70 90 t j junction temperature ( c) retention (years) 250 200 150 100 50 0 50 80 110 300 100 adi specification 100 years min. at t j = 55 c 04741-0-028 figure 65. flash/ee memory data retention flash memory organization the 16kbytes of flash memory provided by the ade7169f16 are segmented into 32 pages of 512 bytes each. it is up to the user to decide which flash memory he would like to allocate for data memory. it is recommended that each page be dedicated solely to program or data memory so that an instance does not arise where the program counter is loaded with data memory instead of an opcode from the program memory or where program memory is erased to update a byte of data memory.
preliminary technical data ade7169f16 rev. prd | page 97 of 140 0x0000 page 0 0x01ff 0x0200 page 1 0x03ff 0x0400 page 2 0x05ff 0x0600 page 3 0x07ff 0x0800 page 4 0x09ff 0x0a00 page 5 0x0bff 0x0c00 page 6 0x0dff 0x0e00 page 7 0x0fff 0x1000 page 8 0x11ff 0x1200 page 9 0x13ff 0x1400 page 10 0x15ff 0x1600 page 11 0x17ff 0x1800 page 12 0x19ff 0x1a00 page 13 0x1bff 0x1c00 page 14 0x1dff 0x1e00 page 15 0x1fff read protect bit 0 read protect bit 1 read protect bit 2 read protect bit 3 0x2000 page 16 0x21ff 0x2200 page 17 0x23ff 0x2400 page 18 0x25ff 0x2600 page 19 0x27ff 0x2800 page 20 0x29ff 0x2a00 page 21 0x2bff 0x2c00 page 22 0x2dff 0x2e00 page 23 0x2fff 0x3000 page 24 0x31ff 0x3200 page 25 0x33ff 0x3400 page 26 0x35ff 0x3600 page 27 0x37ff 0x3800 page 28 0x39ff 0x3a00 page 29 0x3bff 0x3c00 page 30 0x3dff 0x3e00 page 31 0x3fff read protect bit 4 read protect bit 5 read protect bit 6 read protect bit 7 contains protection settings figure 66: flash memory organization the flash memory can be protected from read or write/erase access. the protection is implemented in part of the last page of the flash memory, page 31. four of the bytes from this page are used to set up write/erase protection for each of the pages. another byte is used for configuring read protection of the flash memory. the read protection is selected for groups of four pages. finally, there is a byte used to store the key required for modifying the protection scheme. if any code protection is required, the last page of flash memory must be write/erase protected at a minimum. the implication of write/erase protecting the last page is that the content of the 506 bytes in this page that are available to the user must not change. thus it is recommended that if code protection is enabled, this last page should be used for program memory only if the firmware does not need to be updated in the field. if the firmware must be protected and can be updated at a future date, the last page should be used only for constants used by the program code that will not need to be read during emulation or debug. therefore, pages 0 through 30 are for general program and data memory use. it is recommended that page 31 is used for constants or code that will not need to be updated. note that the last 6 bytes of page 31 are reserved for protecting the flash memory. using the flash memory the 16 kbytes of flash memory are configured as 32 pages, each of 512 bytes. as with the other ade7169f16 peripherals, the interface to this memory space is via a group of registers mapped in the sfr space C see . a data register, edata, holds the byte of data to be accessed. the byte of flash memory is addressed via the eadrh and eadrl registers. the flash sfrs table 83. flash sfrs sfr address default va lu e bit addressable description econ 0xb9 0x00 no flash control flshky 0xba 0xff no flash key protky 0xbb 0xff no flash protection key edata 0xbc 0x00 no flash data protb0 0xbd 0xff no flash w/e protection 0 protb1 0xbe 0xff no flash w/e protection 1 protr 0xbf 0xff no flash read protection eadrl 0xc6 0x00 no flash low address eadrh 0xc7 0x00 no flash high address finally, econ is an 8-bit control register that can be written to with one of seven flash memory access commands to trigger various read, write, erase, and verify functions. figure 67 demonstrates the steps required for access to the flash memory. false: access denied econ=1 econ flshky=0x3b? address decoder flshky eadrl eadrh address flash protection key access allowed? protection decoder command true: access allowed econ=0 figure 67: flash memory read/write/erase protection block diagram econflash/ee memory control sfr programming flash memory is done through the flash memory control flash control sfr (econ, 0xb9). this sfr allows the user to read, write, erase, or verify the 16 kbytes of flash memory. as a method of security, a key must be written to the flshky register to initiate any user access to the flash
ade7169f16 preliminary technical data rev. prd | page 98 of 140 memory. upon completion of the flash memory operation, the flshky register is reset such that it must be written prior to another flash memory operation. requiring the key to be set before an access to the flash memory decreases the likelihood of user code or data being overwritten by a program that has run amuck. the program counter, pc, is held on the instruction where the econ register is written to until the flash memory controller is done performing the requested operation. then the pc increments to continue with the next instruction. any interrupts requests that occur while the flash controller is performing an operation are not handled until the flash operation is complete. all peripherals, such as timers and counters, will continue to operate as configured throughout the flash memory access. table 84. flash control sfr (econ, 0xb9) bit location bit mnemonic default value description 7-0 econ 0 1 write byte: the value in edata is written to the flash memory, at the page address given by eadrh and eardl. note that the byte being addressed must be pre-erased 2 erase page: a 512-byte page of flash memory address is erased. the page is selected by the a ddress in eadrh/l. any address in the page can be written to eadrh/l to select it for erasure. 3 erase all: all 16kbytes of the flash memory are erased. note: this command is used during serial and parallel download modes but should not be executed by user code. 4 read byte: the byte in th e flash memory, addressed by eadrh/l, is read into edata. 5 erase page and write byte: the page that holds the byte addressed by eadrh/l is erased. then, data in edata is written to the byte of flash memory addressed by eadrh/l. 8 protect code: see protecting the flash. table 85. flash key sfr (flshky, 0xba) bit location bit mnemonic default value description 7-0 flshky 0xff the content of this sfr is compared to the flash key C 0x3b. if the two values match the next econ operation is allowed - see protecting the flash. table 86. flash protection key sfr (protky, 0xbb) bit location bit mnemonic default value description 7-0 protky 0xff the content of this sfr is compared to the flash memory location at address 0x3ffa. if the two values ma tch, the update of the write/erase and read protection set up is al lowed - see protecting the flash. if the protection key in the flash is 0xff, protky sfr value is not used for comparison. the protky sfr is also used to write the protection key in the flash. this is done by writing the desired value in protky and write 0x08 in the econ sfr. this opera tion can only be done once. table 87. flash data sfr (edata, 0xbc) bit location bit mnemonic default value description 7-0 edata 0 flash pointer data table 88. flash write/erase pr otection 0 sfr (protb0, 0xbd) bit bit default description
preliminary technical data ade7169f16 rev. prd | page 99 of 140 location mnemonic value 7-0 protb0 0xff this sfr is used to write the write/eras e protection bits for pages 0 to 7 of the flash memory C see protecting the flash. clearing the bit enables the protection. protb0.7: page 7 protb0.6: page 6 protb0.5: page 5 protb0.4: page 4 protb0.3: page 3 protb0.2: page 2 protb0.1: page 1 protb0.0: page 0 table 89. flash write/erase pr otection 1 sfr (protb1, 0xbe) bit location bit mnemonic default value description 7-0 protb1 0xff t his sfr is used to write the write/eras e protection bits for pages 8 to 15 of the flash memory C see protecting the flash. clearing the bit enables the protection. protb1.7: page 15 protb1.6: page 14 protb1.5: page 13 protb1.4: page 12 protb1.3: page 11 protb1.2: page 10 protb1.1: page 9 protb1.0: page 8 table 90. flash read protection sfr (protr, 0xbf) bit location bit mnemonic default value description 7-0 protr 0xff this sfr is used to write the read pr otection bits for pages 0 to 31 of the flash memory C see protecting the fl ash. clearing the bit enables the protection. protr.7: page 28 to 31 protr.6: page 24 to 27 protr.5: page 20 to 23 protr.4: page 16 to 19 protr.3: page 12 to 15 protr.2: page 8 to 11 protr.1: page 4 to 7 protr.0: page 0 to 3 table 91. flash low byte address sfr (eadrl, 0xc6) bit location bit mnemonic default value description 7-0 eadrl 0 flash pointer low byte address this sfr is also used to write the wr ite/erase protection bits for pages 16 to 23 of the flash memory C see prot ecting the flash. clearing the bit enables the protection. eadrl.7: page 23 eadrl.6: page 22 eadrl.5: page 21
ade7169f16 preliminary technical data rev. prd | page 100 of 140 eadrl.4: page 20 eadrl.3: page 19 eadrl.2: page 18 eadrl.1: page 17 eadrl.0: page 16 table 92. flash high byte address sfr (eadrh, 0xc7) bit location bit mnemonic default value description 7-0 eadrh 0 flash pointer high byte address this sfr is also used to write the wr ite/erase protection bits for pages 24 to 31 of the flash memory C see prot ecting the flash. clearing the bit enables the protection. eadrh.7: page 31 eadrh.6: page 30 eadrh.5: page 29 eadrh.4: page 28 eadrh.3: page 27 eadrh.2: page 26 eadrh.1: page 25 eadrh.0: page 24 flash functions sample 8051 code is provided below to demonstrate how to use the flash functions. for these examples, the byte of flash memory, 0x3c00 is accessed. write byte: write f3h into flash memory byte 0x3c00. mov edata, #f3h ; data to be written mov eadrh, #3ch ; setup byte address mov eadrl, #00h mov flshky, #3bh ; write flash security key. mov econ, #01h ; write byte erase page: erase the page containing flash memory byte 0x3c00. mov eadrh, #3ch ; select page through byte address mov eadrl, #00h mov flshky, #3bh ; write flash security key. mov econ, #02h ; erase page erase all: erase all of the 16kbyte flash memory mov flshky, #3bh ; write flash security key. mov econ, #03h ; erase all read byte: read flash memory byte 0x3c00. mov eadrh, #3ch ; setup byte address mov eadrl, #00h mov flshky, #3bh ; write flash security key. mov econ, #04h ; read byte ; data is ready in edata register erase page and write byte: erase the page containing flash memory byte 0x3c00 and then write f3h to that address. note that the other 511 bytes in this page will be erased. mov edata, #f3h ; data to be written mov eadrh, #3ch ; setup byte address mov eadrl, #00h mov flshky, #3bh ; write flash security key. mov econ, #05h ; erase page and then write byte protecting the flash two forms of protection are offered for this flash memory: read protection and write/erase protection. the read protection ensures that any pages that are read protected will not be able to be read by the end user. the write protection ensures that the flash memory cannot be erased or written over. this protects the end system from tampering and can prevent the code from being overwritten in the event of a runaway program. write/erase protection is individually selectable for all of the 32 pages. read protection is selected in groups of 4 pages. see figure 66 for the groupings. the protection bits are stored in the last flash memory locations, addresses 0x3ffa through 0x3fffC see figure 68. 4 bytes are reserved for write/erase protection, 1 byte for read protection and another byte to set the protection security key. the user must enable read and write/erase protection for the last page at a minimum for the entire protection scheme to work.
preliminary technical data ade7169f16 rev. prd | page 101 of 140 remark: the read protection does not prevent movc commands to be executed within the code. there is an additional layer of protection offered by a protection security key. the user can setup a protection security key so that the protection scheme cannot be changed without this key. once the protection key has been configured, it may not be modified. enabling flash protection by code the protection byts in the flash can be programmed using flash controller command and programming econ to 0x08. the eadrh, eadrl, protb1 and protb0 bytes are used in this case to store the data to be written to the 32 bits of write protection. note that the eadrh and eadrl registers are not used as data pointers here, but to store write protection data. protr protky protb0 protb1 eadrl eadrh rp 31-28 rp 27-24 rp 23-20 rp 19-16 rp 15-12 rp 11-8 rp 7-4 rp 3-0 wp 7 wp 6 wp 5 wp 4 wp 3 wp 2 wp 1 wp 0 wp 15 wp 14 wp 13 wp 12 wp 11 wp 10 wp 9 wp 9 wp 23 wp 22 wp 21 wp 20 wp 19 wp 18 wp 17 wp 16 wp 31 wp 30 wp 29 wp 28 wp 27 wp 26 wp 25 wp 24 protection key 0x3fff 0x3ffe 0x3ffd 0x3ffc 0x3ffb 0x3ffa 0x3ff9 0x3e00 figure 68: flash protection in page 31 the sequence for writing the protection bits is: 1. set up the eadrh, eadrl, protb1 and protb0 registers with the write/erase protection bits. when erased, the protection bits default to 1, like any other bit of flash memory. the default protection setting is for no protection. to enable protection, write a 0 to the bits corresponding to the pages that should be protected. 2. set up the protr register with the read protection bits. note that every read protection bit protects four pages. to enable the read protection bit, write a 0 to the bits that should be read protected. 3. to enable the protection key, write to the protky register. if enabled, the protection key will be required to modify the protection scheme. the protection key, flash memory address 0x3ffa defaults to ffh so if the protky register is not written to, it will remain 0xffh. if the protection key is written to, the protky register must be written with this value every time the protection functionality is accessed. note that once the protection key is configured, it cannot be modified. 4. run the protection command by writing 08h to the econ register. 5. reset the chip to activate the new protection. to enable read and write/erase protection for the last page only, use the following 8051 code. writing the flash protection command to the econ register initiates programming the protection bits in the flash. ; enable write/erase protection on the last page only mov eadrh, #07fh mov eadrl, #0ffh mov protb1, #ffh mov protb0, #ffh ; enable read protection on the last four pages only mov protr, #07fh ; set up a protection key of 0a3h. this command can be ; omitted to use the default protection key of 0xff mov protky, #0a3h ; write the flash key to the flshky register to enable flash ; access. the flash access key is not configurable. mov flshky, #3bh ; write flash protection command to the econ register mov econ, #08h enabling flash protection by emulator commands another way to set the flash protection bytes is to use some reserved emulator commands available only in download mode. these commands write directly to the sfrs and can be used to duplicate the operation mentioned in the enabling flash protection by code paragraph. once these flash bytes are written, the part can exit emulation mode by reset and the protections will be effective. this method can be used in production and implemented after downloading the program. the commands used for this operation are an extension of the commands listed in the application note uc004 C understanding the serial download protocol: - command with ascii code i or 0x49 write the data into r0 - command with ascii code f or 0x46 write r0 into the sfr address defined in the data of this command omitting the protocol defined in uc004, the sequence to load protections are similar to the sequence presented mentioned in the enabling flash protection by code paragraph.except that two emulator commands are necessary to replace one assembly
ade7169f16 preliminary technical data rev. prd | page 102 of 140 command. for example to write the protection value in eadrh the two following commands need to be executed: - command i with data = value of protection byte 0x3fff - command f with data = 0xc7 following this protocol, the protection can be written to the flash using the same sequence as mentioned in the enabling flash protection by code paragraph. when the part is reset the protection will be effective. notes on flash protection the flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/erasing. the last page must be read and write/erase protected for the protection scheme to work. to activate the protection settings, the ade7169f16 must be reset after configuring the protection. after configuring protection on the last page and resetting the part, protections that have been enabled can only be removed by mass erasing the flash memory. the protection bits are read and erase protected by enabling read and write/erase protection the last page, but the protection bits are never truly write protected. protection bits can be programmed modified from a 1 to a 0, even after the last page has been protected. in this way, more protection can be added but none can be removed. if a page of code is write/erase protected, it cannot be written over even if an erase all command is issued. the write/erase protected page will not be updated if new code is downloaded. if a page is read protected, this part of the code cannot be read or emulated. the protection scheme is intended to protect the end system. protection should be disabled while developing and emulating code. flash memory timing typical program and erase times for the flash memory are as follows: command bytes affected flash memory timing write byte 1 byte 30us erase page 512 bytes 20ms eraseall 16 kbytes 200ms read byte 1 bytes 100ns erasepage and write byte 512 bytes 21ms verify byte 1 byte 100ns note that the core microcontroller operation is idled until the requested flash memory operation is complete. in practice, this means that even though the flash operation is typically initiated with a two-machine-cycle mov instruction (to write to the flash control sfr (econ, 0xb9)), the next instruction is not executed until the flash/ee operation is complete. this means that the core cannot respond to interrupt requests until the flash/ee operation is complete, although the core peripheral functions such as counter/ timers continue to count as configured throughout this period. in circuit programming serial downloading the ade7169f16 facilitates code download via the standard uart serial port. the parts enter serial download mode after a reset or a power cycle if the sden pin is pulled low through an external 1 k resistor. once in serial download mode, the hidden embedded download kernel executes. this allows the user to download code to the full 16 kbytes of flash memory while the device is in circuit in its target application hardware. protection configured in the last page of the ade7169f16 affects whether flash memory can be accessed in serial download mode. read protected pages cannot be read. write/erase protected pages cannot be written or erased. the configuration bits cannot be programmed in serial download mode.
preliminary technical data ade7169f16 rev. prd | page 103 of 140 timers the ade7169f16 has three 16-bit timer/ counters: timer 0, timer 1, and timer 2. the timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. each timer/counter consists of two 8-bit registers: thx and tlx (x = 0, 1, or 2). all three can be configured to operate either as timers or as event counters. when functioning as a timer, the tlx register is incremented every machine cycle. thus, one can think of it as counting machine cycles. because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency. when functioning as a counter, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin: t0, t1, or t2. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. there are no restrictions on the duty cycle of the external input signal, but, to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. user configuration and control of all timer operating modes is achieved via the sfrs in table 93. table 93. timer sfrs sfr address bit addressable description tcon 0x88 yes timer0 and timer1 control register C see table 95 tmod 0x89 no timer mode registerC see table 94 tl0 0x8a no timer0 lsbC see table 98 tl1 0x8b no timer1 lsbC see table 100 th0 0x8c no timer0 msbC see table 97 th1 0x8d no timer1 msbC see table 99 t2con 0xc8 yes timer2 control register C see table 96 rcap2l 0xca no timer2 reload/capture lsb C see table 104 rcap2h 0xcb no timer2 reload/capture msb C see table 103 tl2 0xcc no timer2 lsb C see table 102 th2 0xcd no timer2 msb C see table 101 timer sfr register list table 94. timer/counter 0 and 1 mode sfr (tmod, 0x89) bit location bit mnemonic default value description 7 gate1 0 timer 1 gating control. set by software to enable time r/counter 1 only while the int1 pin is high and the tr1 control is set. cleared by software to enable timer 1 whenever the tr1control bit is set. 6 c_t1 0 timer 1 timer or counter select bit. set by software to select counte r operation (input from t1 pin). cleared by software to select the timer ope ration (input from internal system clock). timer 1 mode select bits m1 m0 description 0 0 th1 operates as an 8-bit timer/co unter. tl1 serves as 5-bit prescaler. 5-4 t1_m1, t1_m0 00 0 1 16-bit timer/counter. th1 and tl1 ar e cascaded; there is no prescaler.
ade7169f16 preliminary technical data rev. prd | page 104 of 140 1 0 8-bit autoreload timer/counter. th1 holds a value that is to be reloaded into tl1 each time it overflows. 1 1 timer/counter 1 stopped. 3 gate0 0 timer 0 gating control. set by software to enable time r/counter 0 only while the int0 pin is high and the tr0 control bit is set. cleared by software to enable timer 0 whenever the tr0 control bit is set. 2 c_t0 0 timer 0 timer or counter select bit. set by software to the select coun ter operation (input from t0 pin). cleared by software to the select timer ope ration (input from internal system clock). timer 0 mode select bits m1 m0 description 0 0 th0 operates as an 8-bit timer/coun ter. tl0 serves as a 5-bit prescaler. 0 1 16-bit timer/counter. th0 and tl0 ar e cascaded; there is no prescaler. 1 0 8-bit autoreload timer/counter. th0 holds a value that is to be reloaded into tl0 each time it overflows. 1-0 t0_m1, t0_m0 00 1 1 tl0 is an 8-bit timer/counter controlle d by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits. table 95. timer/counter 0 and 1 control sfr (tcon, 0x88) bit location bit addr. bit name default value description 7 0x8f tf1 0 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program coun ter (pc) vectors to the interrupt service routine. 6 0x8e tr1 0 timer 1 run control bit. set by the user to turn on timer/counter 1. cleared by the user to turn off timer/counter 1. 5 0x8d tf0 0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vecto rs to the interrupt service routine. 4 0x8c tr0 0 timer 0 run control bit. set by the user to turn on timer/counter 0. cleared by the user to turn off timer/counter 0. 3 0x8b ie1 1 0 external interrupt 1 (int1 ) flag. set by hardware by a falling edge or by a zero level applied to the ex ternal interrupt pin, int1 , depending on the state of bit it1. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activ ated, the external requesting source controls the request flag rather than the on-chip hardware. 2 0x8a it1 1 0 external interrupt 1 (ie1) trigger type. set by software to specify edge-sensitive detection, that is, 1-to-0 transition. cleared by software to specify level-sen sitive detection, that is, zero level. 1 0x89 ie0 1 0 external interrupt 0 (int0 ) flag. set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, int0 , depending on the statue of bit it0. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activ ated, the external requesting source controls the request flag rather than the on-chip hardware. 0 0x88 it0 1 0 external interrupt 0 (ie0) trigger type. set by software to specify edge-sensitive detection, that is, 1-to-0 transition. cleared by software to specify level-sen sitive detection, that is, zero level. __________________________________________
preliminary technical data ade7169f16 rev. prd | page 105 of 140 2 these bits are not used to control timer/counters 0 and 1, but are used instead to control and monitor the external int0 and int1 interrupt pins. table 96. timer/counter 2 control sfr (t2con, 0xc8) bit location bit addr. bit name default value description 7 0xcf tf2 0 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 cannot be set when either rclk = 1 or tclk = 1. cleared by user software. 6 0xce exf2 0 timer 2 external flag. set by hardware when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 0xcd rclk 0 receive clock enable bit. set by the user to enable the serial port to us e timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by the user to enable timer 1 over flow to be used for the receive clock. 4 0xcc tclk 0 transmit clock enable bit. set by the user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by the user to enable timer 1 over flow to be used for the transmit clock. 3 0xcb exen2 0 timer 2 external enable flag. set by the user to enable a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being us ed to clock the serial port. cleared by the user for timer 2 to ignore events at t2ex. 2 0xca tr2 0 timer 2 start/stop control bit. set by the user to start timer 2. cleared by the user to stop timer 2. 1 0xc9 cnt2 0 timer 2 timer or counter function select bit. set by the user to select the counter function (input from external t2 pin). cleared by the user to select the timer function (input from on-chip core clock). 0 0xc8 cap2 0 timer 2 capture/reload select bit. set by the user to enable captures on ne gative transitions at t2ex if exen2 = 1. cleared by the user to enable autoreloads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. table 97. timer 0 high byte sfr (th0, 0x8c) bit location bit mnemonic default value description 7-0 th0 0 timer 0 data high byte table 98. timer 0 low byte sfr (tl0, 0x8a) bit location bit mnemonic default value description 7-0 tl0 0 timer 0 data high byte table 99. timer 1 high byte sfr (th1, 0x8d) bit location bit mnemonic default value description 7-0 th1 0 timer 1 data high byte table 100. timer 1 low byte sfr (tl1, 0x8b) bit location bit mnemonic default value description 7-0 tl1 0 timer 1 data high byte
ade7169f16 preliminary technical data rev. prd | page 106 of 140 table 101. timer 2 high byte sfr (th2, 0xcd) bit location bit mnemonic default value description 7-0 th2 0 timer 2 data high byte table 102. timer 2 low byte sfr (tl2, 0xcc) bit location bit mnemonic default value description 7-0 tl2 0 timer 2 data high byte table 103. timer 2 reload/capture high byte sfr (racp2h, 0xcb) bit location bit mnemonic default value description 7-0 th2 0 timer 2 reload/capture high byte table 104. timer 2 reload/capture low byte sfr (racp2l, 0xca) bit location bit mnemonic default value description 7-0 tl2 0 timer 2 reload/capture low byte timer 0 and timer 1 timer/counter 0 and 1 data registers each timer consists of two 8-bit registers: timer 0 high byte sfr (th0, 0x8c), timer 0 low byte sfr (tl0, 0x8a), timer 1 high byte sfr (th1, 0x8d) and timer 1 low byte sfr (tl1, 0x8b) these can be used as independent registers or combined into a single 16-bit register, depending on the timers mode configuration C see table 97 to table 100. timer/counter 0 and 1 operating modes this section describes the operating modes for timer/counters 0 and 1. unless otherwise noted, these modes of operation are the same for both timer 0 and timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter. figure 69 shows mode 0 operation. note that the divide-by-12 prescaler is not present on the single-cycle core. 0 4741-0-049 f core control p0.6/t0 gate int0 tr0 tf0 tl0 (5 bits) th0 (8 bits) interrupt c/ t = 0 c/ t = 1 figure 69. timer/counter 0, mode 0 in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag, tf0. tf0 can then be used to request an interrupt. the counted input is enabled to the timer when tr0 = 1 and either gate = 0 or int0 = 1. setting gate = 1 allows the timer to be controlled by external input int0 to facilitate pulse- width measurements. tr0 is a control bit in the timer/counter 0 and 1 control sfr (tcon, 0x88); the gate bit is in timer/counter 0 and 1 mode sfr (tmod, 0x89). the 13-bit register consists of all 8 bits of timer 0 high byte sfr (th0, 0x8c) and the lower 5 bits of timer 0 low byte sfr (tl0, 0x8a). the upper 3 bits of timer 0 low byte sfr (tl0, 0x8a) are indeterminate and should be ignored. setting the run flag (tr0) does not clear the registers. mode 1 (16-bit timer/counter) mode 1 is the same as mode 0 except that the mode 1 timer register runs with all 16 bits. mode 1 is shown in figure 70. control p0.6/t0 gate tr0 tf0 tl0 (8 bits) th0 (8 bits) interrupt 0 4741-0-050 0 int c/ t = 0 c/ t = 1 f core figure 70. timer/counter 0, mode 1
preliminary technical data ade7169f16 rev. prd | page 107 of 140 mode 2 (8-bit timer/counter with autoreload) mode 2 configures the timer register as an 8-bit counter (tl0) with automatic reload as shown in figure 71. overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0, which is preset by software. the reload leaves th0 unchanged. control tf0 tl0 (8 bits) interrupt reload th0 (8 bits) p0.6/t0 gate tr0 0 04741-0-051 in t c/ t = 0 c/ t = 1 f core figure 71. timer/counter 0, mode 2 mode 3 (two 8-bit timer/counters) mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. this configuration is shown in figure 72. tl0 uses the timer 0 control bits c/ t , gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. therefore, th0 then controls the timer 1 interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or it can still be used by the serial interface as a baud rate generator. in fact, it can be used in any application not requiring an interrupt from timer 1 itself. control core clk/12 tf0 tl0 (8 bits) interrupt p0.6/t0 gate tr0 tf1 th0 (8 bits) interrupt f core / 12 tr1 04741-0-052 0 int c/ t = 0 c/ t = 1 f core figure 72. timer/counter 0, mode 3 timer 2 timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it: timer 2 high byte sfr (th2, 0xcd), timer 2 low byte sfr (tl2, 0xcc), timer 2 reload/capture high byte sfr (racp2h, 0xcb) and timer 2 reload/capture low byte sfr (racp2l, 0xca). these are used as both timer data registers and as timer capture/reload registers C see table 101 to table 104. timer/counter 2 operating modes the following sections describe the operating modes for timer/counter 2. the operating modes are selected by bits in the timer/counter 2 control sfr (t2con, 0xc8) as shown in table 96 and table 105. table 105. t2con operating modes rclk (or) tclk cap2 tr2 mode 0 0 1 16-bit autoreload 0 1 1 16-bit capture 1 x 1 baud rate x x 0 off 16-bit autoreload mode autoreload mode has two options that are selected by bit exen2 in timer/counter 2 control sfr (t2con, 0xc8). if exen2 = 0, when timer 2 rolls over, it not only sets tf2 but also causes the timer 2 registers to be reloaded with the 16-bit value in registers timer 2 reload/capture high byte sfr (racp2h, 0xcb) and timer 2 reload/capture low byte sfr (racp2l, 0xca), which are preset by software. if exen2 = 1, timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input t2ex also triggers the 16- bit reload and sets exf2. autoreload mode is shown in figure 73. 16-bit capture mode capture mode has two options that are selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2 = 1, timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. capture mode is shown in figure 74. the
ade7169f16 preliminary technical data rev. prd | page 108 of 140 baud rate generator mode is selected by rclk = 1 and/or tclk = 1. in either case, if timer 2 is used to generate the baud rate, the tf2 interrupt flag does not occur. therefore, timer 2 interrupts do not occur, so they do not have to be disabled. in this mode, the exf2 flag can, however, still cause interrupts, which can be used as a third external interrupt. baud rate generation is described as part of the uart serial port operation in uart serial interface section. p1.4/t2 tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector p1.3/t2e x rcap2l rcap2h 04741-0-053 c/ t2 = 0 c/ t2 = 1 f core figure 73. timer/counter 2, 16-bit autoreload mode tf2 tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector rcap2l rcap2h 04741-0-054 c/ t2 = 0 c/ t2 = 1 f core p1.4/t2 p1.3/t2e x figure 74. timer/counter 2, 16-bit capture mode
preliminary technical data ade7169f16 rev. prd | page 109 of 140 pll the ade7169f16 is intended for use with a 32.768 khz watch crystal. a pll locks onto a multiple of this frequency to provide a stable 4.096 mhz clock for the system. the core can operate at this frequency or at binary submultiples of it to allow power saving wh en maximum core performance is not required. the default core clock is the pll clock divided by 4 or 1.024 mhz. the ade energy measurement clock is derived from the pll clock and is maintained at 4.096/5 mhz, 819.2 khz across all cd settings. the pll is controlled by the cd[2:0] bits in the power control sfr (powcon, 0xc5). to protect erroneous changes to the power control sfr (powcon, 0xc5), a key is required to modify the register. first the powcon key sfr (kyreg, 0xc1) is written with the key, 0xa7, and then a new value is written to the power control sfr (powcon, 0xc5). if the pll loses lock, the mcu is reset and the pllfault bit is set in the peripheral configuration sfr (periph, 0xf4). set the pll_flt_ack bit in the start adc measurement sfr (adcgo, 0xd8) to acknowledge the pll fault, clearing the pllfault flag. pll sfr register list power control sfr (powcon, 0xc5) bit location bit mnemonic default value description 7-5 reserved 0 4 coreoff 0 set this bit to shut down the core if in the psm1 operating mode. 3 reserved controls the core clock frequency, f core . f core =4.096mhz/2 cd cd[2:0] f core (mhz) 0 0 0 4.096 0 0 1 2.048 0 1 0 1.024 0 1 1 0.512 1 0 0 0.256 1 0 1 0.128 1 1 0 0.064 2-0 cd[2:0] 010 1 1 1 0.032 table 106. powcon key sfr (kyreg, 0xc1) bit location bit mnemonic default value description 7-0 kyreg 0 write 0xa7 to the kyreg sfr befo re writing the powcon sfr, to unlock it. peripheral configuration sfr (periph, 0xf4) bit location bit mnemonic default value description 7 rxflag 0 if set, indicates that a rx edge event triggered wakeup from psm2 indicates the power supply that is connected internally to v sw . 0 v sw =v bat 6 vswsource 1 1 v sw =v dd 5 vdd_ok 0 if set, indicates that vdd power supply is ok for operation 4 pll_flt 0 if set, indica tes that pll is not locked 3 reserved 2 extrefen 0 set this bit if an external reference is connected to the refin pin.
ade7169f16 preliminary technical data rev. prd | page 110 of 140 controls the function of the p1.0/rx pin. rxprog [1:0] function 0 0 gpio 0 1 rx with wakeup disabled 1-0 rxprog[1:0] 00 1 1 rx with wakeup enabled start adc measurement sfr (adcgo, 0xd8) bit location bit addr. bit name default value description 7 0xdf pll_ftl_ack 0 set this bit to clear the pll fault bi t, pll_flt in the periph register. a pll fault is generated if a reset was caused because the pll lost lock. 6-3 0xde C 0xdb reserved 0 reserved 2 0xda vsw_adc_go 0 set this bit to initiate a supply vo ltage measurement. this bit will be cleared when the measurement requ est is received by the adc. 1 0xd9 temp_adc_go 0 set this bit to initiate a temperature measurement. this bit will be cleared when the measurement request is received by the adc. 0 0xd8 batt_adc_go 0 set this bit to initiate a battery measur ement. this bit will be cleared when the measurement request is received by the adc.
preliminary technical data ade7169f16 rev. prd | page 111 of 140 rtc - real time clock the ade7169f16 has an embedded real time clock (rtc) C see figure 75. the external 32.768 khz crystal is used as the clock sour ce for the rtc. calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal fre quency over temperature. by default, the rtc is maintained active in all the power saving modes. the rtc counters retain their values thro ugh watchdog resets and external resets and are only reset during a power on reset. 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour iten alarm event 8-bit interval counter intval sfr interval timebase selection mux rtcen 32.768khz crystal its1 its0 equal? calibration rtccomp tempcal midnight event calib r ated 32.768khz figure 75: rtc implementation rtc sfr register list sfr address bit addressable description timecon 0xa1 no rtc configuration hthsec 0xa2 no hundred th of a second counter sec 0xa3 no seconds counter min 0xa4 no minutes counter hour 0xa5 no hours counter intval 0xa6 no alarm interval rtccomp 0xf6 no rtc nominal compensation
ade7169f16 preliminary technical data rev. prd | page 112 of 140 tempcal 0xf7 no rtc temperature compensation table 107. rtc configuration sfr (timecon, 0xa1) bit location bit mnemonic default value description midnight flag 7 midnight 0 this bit is set when the rtc rolls over to 00:00:00:00. it can be cleared by the user to indicate that the midni ght event has been serviced. in twenty- four hour mode, the midnight flag is raised once a day at midnight. twenty-four hour mode 0 256 hour mode. the hour register will roll over from 255 to 0. 1 24 hour mode. the hour regist er will roll over from 23 to 0. 6 tfh 0 note: this bit is retained during a watchd og reset or an external reset. it is reset after a power on reset (por). interval timer timebase selection its[1:0] timebase 0 0 1/128 second 0 1 second 1 0 minute 5-4 its[1:0] 0 1 1 hour interval timer one-time alarm 0 the alarm flag will be set after in tval counts and then another interval count will start. 3 sit 0 1 the alarm flag will be set after one time interval. interval timer alarm flag 2 alarm 0 this bit is set when the configured t ime interval has elapsed. it can be cleared by the user to indicate that the alarm event has been serviced. interval timer enable 0 the interval timer is disabled. th e 8-bit interval timer counter is reset. 1 iten 0 1 set this bit to enable the interv al timer. the rtcen bit must also be set to enable the interval timer. rtc enable. also temperature, ba ttery and supply adc background strobe enable 0 the rtc and interval timer are disabled and the rtc registers are cleared. when this bit is clear, the background adc strobe timer is disabled. 1 the rtc is enabled. the background adc strobe timer is enabled. 0 rtcen 1 note: this bit is retained during a watchd og reset or an external reset. it is reset after a power on reset (por). table 108. hundredths of a second counter sfr (hthsec, 0xa2) bit location bit mnemonic default value description this counter updates every 1/128 second , referenced from the calibrated 32khz clock. it overflows from 127 to 00, incrementing the seconds counter, sec. 7-0 hthsec 0 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por).
preliminary technical data ade7169f16 rev. prd | page 113 of 140 table 109. seconds counter sfr (sec, 0xa3) bit location bit mnemonic default value description this counter updates every second, refe renced from the calibrated 32khz clock. it overflows from 59 to 00, incrementing the minutes counter, min. 7-0 sec 0 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por). table 110. minutes counter sfr (min, 0xa4) bit location bit mnemonic default value description this counter updates every minute, refe renced from the calibrated 32khz clock. it overflows from 59 to 00, incrementing the hours counter, hour. 7-0 min 0 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por). table 111. hours counter sfr (hour, 0xa5) bit location bit mnemonic default value description this counter updates every hour, refe renced from the calibrated 32khz clock. if the tfh bit in the rtc conf iguration sfr (timecon, 0xa1) is set, the hour sfr overflows from 23 to 00, setting the midnight bit and creating a pending rtc interrupt. if the tfh bit in the rtc configuration sfr (timecon, 0xa1) is clear, the ho ur sfr overflows from 255 to 00, setting the midnight bit and creating a pending rtc interrupt. 7-0 hour 0 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por). table 112. alarm interval sfr (intval, 0xa6) bit location bit mnemonic default value description 7-0 intval 0 the interval timer counts according to the timebase es tablished in the its[1:0] bits of the rtc configuration sfr (timecon, 0xa1). once the number of counts is equal to intval, the alarm flag is set and a pending rtc interrupt is created. note that the interval counter is 8-bits so it could count up to 255 seconds, for example. table 113. rtc nominal compensation sfr (rtccomp, 0xf6) bit location bit mnemonic default value description the rtccomp sfr holds the nominal rtc compensation value at 25 c. 7-0 rtccomp 0 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por). table 114. rtc temperature compensation sfr (tempcal, 0xf7) bit location bit mnemonic default value description 7-0 tempcal 0 the tempcal sfr is adjusted based on the temerature read in the tempadc to calibrate the rtc over te mperature. this allows the external crystal shift to be compen sated over temperature.
ade7169f16 preliminary technical data rev. prd | page 114 of 140 note: this register is retained during a watchdog reset or an external reset. it is reset after a power on reset (por). read and write operations writing the rtc registers the rtc circuitry runs off a 32.768 khz clock. it takes up to two 32 khz clock cycles from when the mcu writes an rtc register until it is successfully updated in the rtc. reading the rtc counter sfrs the rtc cannot be stopped to read the current time because stopping the rtc would introduce an error in its timekeeping. so the rtc is read on the fly. therefore the counter registers must be checked for overflow. this can be accomplished through the following 8052 assembly code: readagain: mov r0, hthsec ; using bank 0 mov r1, sec mov r2, min mov r3, hour mov a, hthsec cjne a, 00h, readagain ; 00h is r0 in bank 0 rtc modes the rtc can be configured in a 24 hour mode or a 256 hour mode. a midnight event is generated when the rtc hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the tfh bit is set in the rtc configuration sfr (timecon, 0xa1). the midnight event sets the midnight flag in the rtc configuration sfr (timecon, 0xa1) and a pending rtc interrupt is created. the rtc midnight event will wake the 8052 mcu core if the mcu is asleep in psm2 when the midnight event occurs. in the 24 hour mode, the midnight event is generated once a day, at midnight. the 24 hour mode is useful for updating a software calendar to keep track of the current day. the 256 hour mode will result in power savings during extended operation in psm2 because the mcu core will be wpken less frequently. rtc interrupts the rtc midnight and alarm interrupts are enabled by setting the eti bit in the interrupt enable and priority 2 sfr (ieip2, 0xa9). when a midnight or alarm event occurs, a pending rtc interrupt is generated. if the rtc interrupt is enabled, the program will vector to the rtc interrupt address and the pending interrupt will be cleared. if the rtc interrupt is disabled, then the rtc interrupt will remain pending until the rtc interrupt is enabled. then the program will vector to the rtc interrupt address. the midnight and alarm flags are set when the midnight and alarm events occur, respectively. the user should manage these flags to keep track of which event caused an rtc interrupt by servicing the event and clearing the appropriate flag in the rtc isr. interval timer alarm the rtc can be used as an interval timer. when the interval timer is enabled by setting the iten bit in the rtc configuration sfr (timecon, 0xa1), the interval timer clock source selected by the its1 and its0 bits is passed through to an 8-bit counter. this counter increments on every interval timer clock pulse until the 8-bit counter is equal to the value in the alarm interval sfr (intval, 0xa6). then an alarm event is generated, setting the alarm flag and creating a pending rtc interrupt. if the sit bit in the rtc configuration sfr (timecon, 0xa1) is clear then the 8-bit counter is cleared and starts counting again. if the sit bit is set then the 8-bit counter is held in reset after the alarm occurs. the rtc alarm event will wake the 8052 mcu core if the mcu is in psm2 when the alarm event occurs. rtc calibration the rtc provides registers to calibrate the nominal external crystal frequency and its variation over temperature. up to 248ppm frequency error can be calibrated out by the rtc circuitry, which adds or subtracts pulses from the external crystal signal. the nominal crystal frequency should be calibrated with the rtccomp register so that the clock going into the rtc is precisely 32.768 khz at 25 c. the rtc temperature compensation sfr (tempcal, 0xf7) is used to compensate for the external crystal drift over temperature by adding or subtracting additional pulses based on temperature. the lsb of each rtc compensation register represents a 2ppm frequency error. the rtc compensation circuitry adds the rtc temperature compensation sfr (tempcal, 0xf7) and the rtc nominal compensation sfr (rtccomp, 0xf6) to determine how much compensation is required and the sum of these two registers is limited to 248ppm. calibration flow: tbd during calibration, user software writes the rtc with the current time. the rtc should be stopped to perform this setup. the user should wait at least one 32 khz clock period after clearing the rtcen bit in the rtc configuration sfr
preliminary technical data ade7169f16 rev. prd | page 115 of 140 (timecon, 0xa1) to ensure that the rtc is stopped before writing the counter registers. then the rtc should be started again by setting the rtcen bit. note that it takes up to two 32 khz clock periods to update the rtc counter sfrs. this can be accomplished using the following 8052 assembly code where the current time is held in r0 through r3. setuprtc: mov timecon,#040h ; stop the rtc ; wait at least one 32 khz clock period (30.5us) mov tcon, #03h ; tl0 is an 8-bit timer mov tl0,#00h ; waits 62.5us at 4.096mhz clr tf0 ; clear overflow flag setb tr0 ; start timer0 timeout: jnz tf0, timeout mov hthsec, r0 ; using bank 0 mov sec, r1 mov min, r2 mov hour, r3 mov timecon, #041h ; start the rtc
ade7169f16 preliminary technical data rev. prd | page 116 of 140 uart serial interface the ade7169f16 uart can be configured in one of four modes: - shift register with baud rate fixed at f core /12 - 8-bit uart with variable baud rate - 9- bit uart with baud rate fixed at f core /64 or f core /32 - 9 bit uart with variable baud rate variable baud rates are defined by using an internal timer to generate any rate between 300 and 115200 bauds/s. the uart serial interface provided in the ade7169f16 is a full-duplex serial interface. it is also receive buffered, by storing the first received byte in a receive buffer until the reception of the second byte is complete. the physical interface to the uart is provided via the rxd (p1.0) and txd (p1.1) pins, while the firmware interface is through the sfrs presented in table 115. both the serial port receive and transmit registers are accessed through the sbuf sfr (sfr address = 0x99). writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. an enhanced uart mode is offered by using uart timer and providing enhanced frame error, break error and overwrite error detection. this mode is enabled by setting the exten bit in the cfg sfrsee the uart additional features section. the sbaudt and sbaudf sfr are used to configure uart timer and to indicate the enhanced uart errors. uart sfr register list table 115. serial port sfrs sfr address bit addressable description scon 0x98 yes serial communications control register C see table 116 sbuf 0x99 no serial port buffer C see table 117 sbaudt 0x9e no enhanced error checking C see table 118 sbaudf 0x9d no enhanced fractional divider C see table 119 table 116. scon sfr bit description sfr (scon, 0x98) bit location bit addr. bit name default va lu e description uart serial mode select bits. these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode. 0 0 mode 0: shift register, fixed baud rate (f core /12). 0 1 mode 1: 8-bit uart, variable baud rate. 1 0 mode 2: 9-bit uart, fixed baud rate (f core /32) or (f core /16). 7-6 0x9f, 0x9e sm0, sm1 00 1 1 mode 3: 9-bit uart, variable baud rate. 5 0x9d sm2 0 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3 and framing error detection in mode 1. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri is not activated if a valid stop bit was not received. if sm2 is cleared, ri is set as soon as the byte of data is received.
preliminary technical data ade7169f16 rev. prd | page 117 of 140 in modes 2 or 3, if sm2 is set, ri is not activated if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri is set as soon as the byte of data is received. 4 0x9c ren 0 serial port receive enable bit. set by user software to enable serial port reception. cleared by user software to disable serial port reception. 3 0x9b tb8 0 serial port transmit (bit 9). the data loaded into tb8 is the ninth data bit transmitted in modes 2 and 3. 2 0x9a rb8 0 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched into rb8. for mode 1, the stop bit is latched into rb8. 1 0x99 ti 0 serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0 0x98 ri 0 serial port receive interrupt flag. set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by user software. table 117. serial port buffer sfr (sbuf, 0x99) bit location bit mnemonic default value description 7-0 sbuf 0 serial port data buffer table 118. enhanced serial baud rate control sfr (sbaudt, 0x9e) bit location bit mnemonic default value description 7 owe 0 overwrite error. this bit is set when new data is received and ri=1. it indicates that sbuf was not read before the next charac ter was transferred in, causing the prior sbuf data to be lost. 6 fe 0 frame error. this bit is set when the recei ved frame did not have a valid stop bit. this bit is read only and updated eve ry time a frame is received. 5 be 0 break error. this bit is set whenever the recei ve data line (rx) is low for longer than a full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half a stop bit. this bit is updated every time a frame is received. 4-3 sbth1, sbth0 0 extended divider ratio fo r baud rate setting as shown in table 120 2, 1, 0 div2, div1, div0 0 binary divider div2 div1 div0 0 0 0 divide by 1. see table 120. 0 0 1 divide by 2. see table 120. 0 1 0 divide by 4. see table 120. 0 1 1 divide by 8. see table 120. 1 0 0 divide by 16. see table 120. 1 0 1 divide by 32. see table 120. 1 1 0 divide by 64. see table 120. 1 1 1 divide by 128. see table 120.
ade7169f16 preliminary technical data rev. prd | page 118 of 140 table 119. uart timer fractional divider sfr (sbaudf, 0x9d) bit location bit mnemonic default value description 7 uartbauden 0 uart baud rate enable set to enable uart timer to generate the baud rate. when set, pcon.7, t2con.4, and t2con.5 are ignored. cleare d to let the baud rate be generated as per a standard 8052. 6 ---- not implemented. write dont care. 5 sbaudf.5 0 uart timer fractional divider bit 5. 4 sbaudf.4 0 uart timer fractional divider bit 4. 3 sbaudf.3 0 uart timer fractional divider bit 3. 2 sbaudf.2 0 uart timer fractional divider bit 2. 1 sbaudf.1 0 uart timer fractional divider bit 1. 0 sbaudf.0 0 uart timer fractional divider bit 0. table 120. common baud rates using uart timer with a 4.096 mhz fll clock ideal baud cd sbth div sbaudt sbaudf % error 115200 0 0 1 01h 87h + 0.16 115200 1 0 0 00h 87h + 0.16 57600 0 0 2 02h 87h + 0.16 57600 1 0 1 01h 87h + 0.16 38400 0 0 2 02h abh - 0.31 38400 1 0 1 01h abh - 0.31 38400 2 0 0 00h abh - 0.31 19200 0 0 3 03h abh - 0.31 19200 1 0 2 02h abh - 0.31 19200 2 0 1 01h abh - 0.31 19200 3 0 0 00h abh - 0.31 9600 0 0 4 04h abh - 0.31 9600 1 0 3 03h abh - 0.31 9600 2 0 2 02h abh - 0.31 9600 3 0 1 01h abh - 0.31 9600 4 0 0 00h abh - 0.31 4800 0 0 5 05h abh - 0.31 4800 1 0 4 04h abh - 0.31 4800 2 0 3 03h abh - 0.31 4800 3 0 2 02h abh - 0.31 4800 4 0 1 01h abh - 0.31 4800 5 0 0 00h abh - 0.31 2400 0 0 6 06h abh - 0.31 2400 1 0 5 05h abh - 0.31 2400 2 0 4 04h abh - 0.31 2400 3 0 3 03h abh - 0.31 2400 4 0 2 02h abh - 0.31 2400 5 0 1 01h abh - 0.31 2400 6 0 0 00h abh - 0.31
preliminary technical data ade7169f16 rev. prd | page 119 of 140 300 0 2 7 17h abh - 0.31 300 1 1 7 0fh abh - 0.31 300 2 0 7 07h abh - 0.31 300 3 0 6 06h abh - 0.31 300 4 0 5 05h abh - 0.31 300 5 0 4 04h abh - 0.31 300 6 0 3 03h abh - 0.31 300 7 0 2 02h abh - 0.31 uart operation modes mode 0 (shift register with baud rate fixed at fcore /12) mode 0 is selected when the sm0 and sm1 bits in the scon sfr are clear. in this shift register mode, serial data enters and exits through rxd. txd outputs the shift clock. the baud rate is fixed at f core /12. eight data bits are transmitted or received. transmission is initiated by any instruction that writes to sbuf. the data is shifted out of the rxd line. the 8 bits are transmitted with the least significant bit (lsb) first. reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0. when ri is cleared, the data is clocked into the rxd line, and the clock pulses are output from the txd line as shown in figure 76. rxd (data out) txd (shift clock) data bit 0 data bit 1 data bit 6 data bit 7 04741-0-055 figure 76. 8-bit shift register mode mode 1 (8-bit uart, variable baud rate) mode 1 is selected by clearing sm0 and setting sm1. each data byte (lsb first) is preceded by a start bit (0) and followed by a stop bit (1). therefore, each frame consists of 10 bits transmitted on txd or received on rxd. the baud rate is set by a timer overflow rate. timer 1 or timer 2 can be used to generate baud rates or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. there is also a dedicated timer for baud rate generation, uart timer, which has a fractional divisor to precisely generate any baud ratesee the uart timer generated baud rates section. transmission is initiated by a write to sbuf. next a stop bit (a 1) is loaded into the 9th bit position of the transmit shift register. the data is output bit-by-bit until the stop bit appears on txd and the transmit interrupt flag (ti) is automatically set as shown in figure 77. figure 77. 8-bit variable baud rate reception is initiated when a 1-to-0 transition is detected on rxd. assuming that a valid start bit is detected, character reception continues. the 8 data bits are clocked into the serial port shift register. all of the following conditions must be met at the time the final shift pulse is generated to receive a character: ? if the extended uart is disabled (exten=0 in the cfg sfr), ri must be zero to receive a character. this ensures that the data in sbuf will not be overwritten if the last received character has not been read. ? if frame error checking is enabled by setting sm2, the received stop bit must be set to receive a character. this ensures that every character received comes from a valid frame, with both a start and a stop bit) if any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag, ri, is not set. if the received frame has met the above criteria, the following events occur: ? the 8 bits in the receive shift register are latched into sbuf. ? the 9th bit (stop bit) is clocked into rb8 in scon. ? the receiver interrupt flag (ri) is set. mode 2 (9- bit uart with baud fixed at f core /64 or f core /32) mode 2 is selected by setting sm0 and clearing sm1. in this mode, the uart operates in 9-bit mode with a fixed baud rate. the baud rate is fixed at f core /64 by default, although by setting the smod bit in pcon, the frequency can be doubled to f core /32. eleven bits are transmitted or received: a start bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1). the 9th bit is most often used as a parity bit or as part of a multiprocessor communication protocol, although it can be used for anything, including a ninth data bit if required. to use the 9 th data bit as part of a communication protocol for a txd ti (scon.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i.e., ready for more data 04741-0-056
ade7169f16 preliminary technical data rev. prd | page 120 of 140 multiprocessor network such as rs-485, the 9 th bit is set to indicate that the frame contains the address of the device that the master would like to communicate with. the devices on the network are always listening for a packet with the 9 th bit set and are configured such that if the 9 th bit is clear, the frame will not be valid and a receive interrupt will not be generated. if the 9 th bit is set, all of the devices on the network will receive the address and get a receive character interrupt. the devices will examine the address and if it matches a devices preprogrammed address, the device will configure itself to listen to all incoming frames, even those with the 9 th bit clear. since the master has initiated communication with that device, all the following packets with the 9 th bit clear are intended specifically for the addressed device until another packet with the 9 th bit set is received. if the address does not match, the device will continue listening for address packets. to transmit, the 8 data bits must be written into sbuf. the ninth bit must be written to tb8 in scon. when transmission is initiated, the 8 data bits from sbuf are loaded into the transmit shift register (lsb first). the 9 th data bit, held in tb8, is loaded into the 9th bit position of the transmit shift register. the transmission starts at the next valid baud rate clock. the transmit interrupt flag, ti, is set as soon as the transmission has completed, when the stop bit appears on txd. all of the following conditions must be met at the time the final shift pulse is generated to receive a character: ? if the extended uart is disabled (exten=0 in the cfg sfr), ri must be zero to receive a character. this ensures that the data in sbuf will not be overwritten if the last received character has not been read. ? if multiprocessor communication is enabled by setting sm2, the received 9 th bit must be set to receive a character. this ensures that only frames with the 9 th bit set, frames that contain addresses, generate a receive interrupt. if any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag, ri, is not set. reception for mode 2 is similar to that of mode 1. the 8 data bytes are input at rxd (lsb first) and loaded onto the receive shift register. if the received frame has met the above criteria, the following events occur: ? the 8 bits in the receive shift register are latched into sbuf. ? the 9th data bit is latched into rb8 in scon. ? the receiver interrupt flag (ri) is set. mode 3 (9-bit uart wi th variable baud rate) mode 3 is selected by setting both sm0 and sm1. in this mode, the 8051 uart serial port operates in 9-bit mode with a variable baud rate. the baud rate is set by a timer overflow rate. timer 1 or timer 2 can be used to generate baud rates or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. there is also a dedicated timer for baud rate generation, uart timer, which has a fractional divisor to precisely generate any baud ratesee the uart timer generated baud rates section. the operation of the 9-bit uart is the same as for mode 2, but the baud rate can be varied. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 when ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. uart baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed: mode 0 baud rate = ? ? ? ? ? ? 12 core f mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/32 of the core clock. if smod = 1, the baud rate is 1/16 of the core clock: mode 2 baud rate = 32 2 smod f core modes 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the overflow rate of the timer generating the baud rate: either timer 1 or timer 2 or the dedicated baud rate generator, uart timer, which has an integer and fractional divisor. timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: modes 1 and 3 baud rate = 32 2 smod timer 1 overflow rate the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation, and in any of its three running modes. in the most typical application, it is configured for timer operation in autoreload mode (high nibble of tmod = 0010 binary). in that case, the baud rate is given by the formula modes 1 and 3 baud rate = ) 1 256 ( 32 2 th f core smod ? timer 2 generated baud rates baud rates can also be generated by using timer 2. using timer 2 is similar to using timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. because timer 2 has a 16-bit autoreload mode, a wider range of baud rates is
preliminary technical data ade7169f16 rev. prd | page 121 of 140 possible. modes 1 and 3 baud rate = 16 1 timer 2 overflow rate therefore, when timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. it increments six times faster than timer 1, and, therefore, baud rates six times faster are possible. because timer 2 has 16-bit autoreload capability, very low baud rates are still possible. timer 2 is selected as the baud rate generator by setting the tclk and/or rclk in t2con. the baud rates for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer 2 into its baud rate generator mode as shown in figure 78. in this case, the baud rate is given by the formula modes 1 and 3 baud rate = () [] () l rcap h rcap f core 2 : 2 65536 16 ? f core t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin transition detector exf 2 timer 2 interrupt note: availability of additional external interrupt rcap2l rcap2h timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow c/ t2 = 0 c/ t2 = 1 04741-0-057 figure 78. timer 2, uart baud rates uart timer generated baud rates the high integer dividers in a uart block mean that high speed baud rates are not always possible. also, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the uart is required. to address this problem, the ade7169f16 has a dedicated baud rate timer (uart timer) specifically for generating highly accurate baud rates. uart timer can be used instead of timer 1 or timer 2 for generating very accurate high speed uart baud rates including 115200. uart timer also allows a much wider range of baud rates to be obtained. in fact, every desired bit rate from 12 bps to 393216 bps can be generated to within an error of 0.8%. uart timer also frees up the other three timers, allowing them to be used for different applications. a block diagram of uart timer is shown in figure 79. ? (1 + sbaudf/64) uart timer rx/tx clock f core uartbauden rx cloc k tx clock timer 1/timer 2 rx clock fractional divider 0 0 1 1 timer 1/timer 2 tx clock ? 32 ? 2 d iv+sbth figure 79. uart timer, uart baud rate two sfrs enhanced serial baud rate control sfr (sbaudt, 0x9e) and uart timer fractional divider sfr (sbaudf, 0x9d) are used to control uart timer. sbaudt is the baud rate control sfr; it sets up the integer divider (div) and the extended divider (sbth) for uart timer.
ade7169f16 preliminary technical data rev. prd | page 122 of 140 the appropriate value to write to the div[2:0] and sbth[1:0] bits can be calculated using the following formula where f core is defined in powcon sfr. note that the div value must be rounded down to the nearest integer. div+ sbth = () 2 log 16 log ? ? ? ? ? ? ? ? rate baud f core sbaudf is the fractional divider ratio required to achieve the required baud rate. the appropriate value for sbaudf can be calculated with the following formula: sbaudf = ? ? ? ? ? ? ? ? ? ? ? + 1 2 16 64 rate baud f sbth div core note that sbaudf should be rounded to the nearest integer. once the values for div and sbaudf are calculated, the actual baud rate can be calculated with the following formula: actual baud rate = ? ? ? ? ? ? + ? ? + 64 1 2 16 sbaudf f sbth div core for example, to get a baud rate of 9600 while operating at a core clock frequency of 4.096 mhz, with the pll cd bits equal to zero, div + sbth = log(4096000/(16 9600))/log2 = 4.74 = 4 note that the div result is rounded down. sbaudf = 64*(4096000/(16*2 3 *9600)-1) = 42.67 = 2bh therefore, the actual baud rate is 9570 bps, which gives an error of 0.31%. uart additional features enhanced error checking the extended uart provides frame error, break error and overwrite error detection. framing errors occur when a stop bit is not present at the end of the frame. a missing stop bit implies that the data in the frame may not have been received properly. break error detection indicates if the rx line has been low for longer than a 9-bit frame. it indicates that the data just received, a zero, or nul character, is not valid because the master has disconnected. overwrite error detection indicates if the received data isnt read fast enough and as result, a byte of data has been lost. the 8052 standard uart offers frame error checking for an 8- bit uart through the sm2 and rb8 bits. setting the sm2 bit prevent frames without a stop bit from being received. the stop bit is latched into the rb8 bit in the scon register. this bit can be examined to determine if a valid frame was received. the 8052 does not however, provide frame error checking for a 9-bit uart. this enhanced error checking functionality is available through the frame error bit, fe in the sbaudt sfr. the fe bit will be set on framing errors for both 8-bit and 9-bit uarts. rx d0 d1 d2 d3 d4 d5 d6 d7 st a r t stop ri fe exten=1 figure 80: uart timing in mode 1 rx d0 d1 d2 d3 d4 d5 d6 d7 st a r t stop d8 ri fe exten=1 figure 81: uart timing in modes 2 and 3 the 8052 standard uart does not provide break error detection. however for an 8-bit uart, it can be determined that a break error occurred if the received character is zero, a nul character, and there was no stop bit because the rb8 bit is low. break error detection is not possible for a 9-bit 8052 uart because the stop bit is not recorded. the ade7169f16 enhanced break error detection is available through the be bit in the sbaudt sfr. the 8052 standard uart prevents overwrite errors by not allowing a character to be received if the ri, receive interrupt flag, is set. however, it does not indicate if a character has been lost because the ri bit was set when the frame was received. the enhanced uart overwrite error detection provides this information. when the enhanced 8052 uart is enabled, a frame will be received regardless of the state of the ri flag. if ri=1 when a new byte is received, the byte in scon is overwritten, and the overwrite error flag will be set. the overwrite error flag will be cleared when sbuf is read. the extended uart is enabled by setting the exten bit in the cfg sfr. uart txd signal modulation there is an internal 38 khz signal which can be ored with the uart transmit signal for use in remote control applications see the 38 khz modulation section. one of the events that can wake the mcu from sleep mode is activity on the uart rx pinsee the 3.3v peripherals and wa k e up eve nt s s e c t i on .
preliminary technical data ade7169f16 rev. prd | page 123 of 140 serial peripheral interface interface (spi) the ade7169f16 integrates a complete hardware serial peripheral interface on-chip. the spi interface is full duplex so that eight bits of data are synchronously transmitted and received simultaneously. this spi implementation is double buffered. this allows the user to read the last byte of received data while a new byte is shifted in. the next byte to be transmitted can be loaded while the current byte is shifted out. the spi port can be configured for master or slave operation. the physical interface to the spi is done via miso (p0.3), mosi (p0.2), sclk (p0.4) and ss (p0.5) pins, while the firmware interface is done via the spi configuration register sfr (spimod1, 0xe8) , spi configuration register sfr (spimod2, 0xe9) , spi interrupt status regi ster sfr (spistat, 0xea) , spi/i2c transmit buffer sfr (spi2ctx, 0x9a) and spi receive buffer sfr (spi2crx, 0x9b) . note that the spi pins are shared with the i 2 c pins. therefore, the user can enable only one interface at a time. the scps bit in the cfg sfr selects which peripheral is active. spi sfr register list sfr address name r/w length default value description 0x9a spi2ctx w 8 spi data out register 0x9b spi2crx r 8 0 spi data in register 0xe8 spimod1 r/w 8 0x10 spi configuration register 0xe9 spimod2 r/w 8 0 spi configuration register 0xea spi2cstat r/w 8 0 spi/i2c interrupt status register table 121: spi sfr register list table 122. spi/i2c transmit buffer sfr (spi2ctx, 0x9a) bit location bit mnemonic default value description 7-0 spi2ctx 0 spi or i2c transmit buffer when spi2ctx sfr is written, its content is transfered to the transmit fifo input. when a write is requested, the fifo o utput is sent on the spi or i2c bus. table 123. spi receive buffer sfr (spi2crx, 0x9b) bit location bit mnemonic default value description 7-0 spi2crx 0 spi or i2c receive buffer when spi2crx sfr is read, one byte from the receive fifo output is transfered to spi2crx sfr. a new data from the spi or i2c bus is written to the fifo input. table 124. spi configuration register sfr (spimod1, 0xe8) bit location bit addr. bit name default value description 7-5 0xef C 0xee reserved 0 reserved 5 0xed intmod 0 spi interrupt mode 0: spi interrupt set when spi rx buffer full 1: spi interrupt set when spi tx buffer empty 0xec master mode: ss output control. see figure 82. 0 the ss is held low while this bit is clea r. this allows manual chip select control using the ss pin. single byte read or write: the ss will go low during a single byte transmission and then return high. 4 auto_ss 1 1 continuous transfer: the ss will go low during the duration of the multi- byte continuous transfer and then return high. 3 0xeb sse 0 slave mode: ss input enable
ade7169f16 preliminary technical data rev. prd | page 124 of 140 when this bit is set to logic one, the ss pin is defined as the slave select input pin for the spi slave interface 0xea receive buffer overflow write enable 0 if the spirx sfr has not been re ad when a new data byte is received, the new byte will be discarded. 2 rxofw 0 1 if the spirx sfr has not been re ad when a new data byte is received, the new byte will overwrite the old data. 1-0 0xe9 C 0xe8 spir[1:0] 0 master mode: spi sclk frequency [1:0] 00 f core / 8 = 512khz if f core = 4.096mhz 01 f core / 16 = 256khz if f core = 4.096mhz 10 f core / 32 = 128khz if f core = 4.096mhz 11 f core / 64 = 64khz if f core = 4.096mhz table 125. spi configuration register sfr (spimod2, 0xe9) bit location bit mnemonic default value description master mode: spi continuous transfer mode enable bit 0 the spi interface will stop after one byte is transferred and ss will be deasserted. a new data transfer can be intiated after a stalled period. 7 spicont 0 1 t he spi interface will continue transfe rring data until no valid data is availbale in the spitx sfr. ss will remain asserted until spitx sfr and the transmit shift register is empty. spi interface enable bit 0 the spi interface is disabled. 6 spien 0 1 the spi interface is enabled spi open drain outputs configuration bit 0 internal pull-up resistors ar e connected to the spi outputs 5 spiodo 0 1 the spi outputs are open-drain and need external pull-up resistors spi master mode enable bit 0 the spi interface is defined as a slave 4 spims_b 0 1 the spi interface is defined as a master spi clock polarity configuration bit C see figure 84. 0 the default state of sclk is low an d the first sclk edge is rising. depending on spicpha bit, the spi data output changes state on the falling or rising edge of sclk while the spi data input is sampled on the rising or falling edge of sclk. 3 spicpol 0 1 the default state of sclk is high and the first sclk edge is falling. depending on spicpha bit, the spi data output changes state on the rising or falling edge of sclk while the spi data input is sampled on the falling or rising edge of sclk. spi clock phase configuration bit C see figure 84. 0 the spi data output changes state when ss goes low, at the second edge of sclk and then every two subsequent edges while the spi data input is sampled at the fi rst sclk edge and then every two subsequent edges. 2 spicpha 0 1 t he spi data output changes state at the first edge of sclk and then every two subsequent edges while th e spi data input is sampled at the second sclk edge and then every two subsequent edges. 1 spilsbf 0 master mode: lsb first configuration bit
preliminary technical data ade7169f16 rev. prd | page 125 of 140 0 the msb of the spi outp uts is transmitted first 1 the lsb of the spi outp uts is transmitted first transfer and interrupt mode of the spi interface. 0 transfer is initiated when data is re ad from spirx sfr and an interrupt is generated when there is new data in the spirx sfr. 0 timode 0 1 transfer is initiated when data is written to the spitx sfr and an interrupt is generated when the spitx sfr is empty. table 126. spi interrupt status register sfr (spistat, 0xea) bit location interrupt flag default value description spi peripheral busy flag 0 the spi peripheral is idle 7 busy 0 1 the spi peripheral is busy transferring data in slave or master mode. spi multi-master error flag 0 a multiple master error has not occurred. 6 mmerr 0 1 if the ss_en bit is set, enabling the slave select input and the ss is asserted while the spi peripheral is transferring data as a master, then this flag is raised to indicate the error. spi receive overflow error flag. reading the spirx sfr will clear this bit. spir xof timode 0 x the spirx register contains valid data 5 spirxof 0 1 1 this bit is set if the spirx register is not read before the end of the next byte transfer. if the rxof_e n bit is set and this condition occurs, spirx will be overwritten. spi receive mode interrupt flag. reading the spirx sfr will clear this bit. spirxi rq timode 0 x the spirx register does not contain new data. 1 0 this bit is set when the spirx re gister contains new data. if the spi/i2c interrupt is enabled, an interrupt will be generated when this bit is set. if the spirx regist er isnt read before the end of the current byte transfer, the transfer will stop and the ss will be deasserted. 4 spirxirq 0 1 1 the spirx register contains new data. 3 spirxbf 0 status bit for spi rx buffer. when set the rx fifo is full. a read of the spirx will clear this flag 2 spitxuf 0 status bit for spi tx buffer. wh en set the tx fifo is underflo wing and data can be write into spitx. a read of the spistat sfr or a write to the spitx sfr will clear this flag. spi transmit mode interrupt flag. writing new data to the spitx sfr will clear this bit. spitxirq timode 0 x the spitx register is full. 1 0 the spitx register is empty. 1 spitxirq 0 1 1 this bit is set when the spitx re gister is empty. if the spi/i2c interrupt is enabled, an interrupt will be generated when this bit is set. if new data isnt written into the spitx sfr before the end of the current b yte transfer, the transfer will stop and the ss will be deasserted.
ade7169f16 preliminary technical data rev. prd | page 126 of 140 0 spitxbf 0 status bit for spi tx buffer. when set, the spi tx buffer is full. spi pins miso (master in, slave out data i/o pin) the miso pin is configured as an input line in master mode and as an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out).the data is transferred as byte-wide (8- bit) serial data, msb first. mosi (master out, slave in pin) the mosi pin is configured as an output line in master mode and as an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in).the data is transferred as byte-wide (8- bit) serial data, msb first. sclk (serial clock i/o pin) the master serial clock (sclk) is used to synchronize the data being transmitted and received through the mosi and miso data lines. the sclk pin is configured as an output in master mode and as an input in slave mode. in master mode, the bit rate, polarity, and phase of the clock are controlled by the spi configuration register sfr (spimod1, 0xe8) and spi configuration register sfr (spimod2, 0xe9) . in slave mode, the spi configuration register sfr (spimod2, 0xe9) must be configured with the phase and polarity of the expected input clock. in both master and slave modes, the data is transmitted on one edge of the sclk signal and sampled on the other. it is important, therefore, that cpha and cpol are configured the same for the master and slave devices. ss (slave select pin) in spi slave mode, a transfer is initiated by the assertion of ss low. the spi port will then transmit and receive 8-bit data until the data is concluded by deassertion of ss . in slave mode, ss is always an input. in spi master mode, the ss can be used to control data transfer to a slave device. in the automatic slave select control mode, the ss is asserted low to select the slave device and then raised to deselect the slave device after the transfer is complete. automatic slave select control is enabled by setting the auto_ss bit in the spi configuration register sfr (spimod1, 0xe8) . in a multi-master system, the ss can be configured as an input so that the spi peripheral can operate as a slave in some situations and as a master in other situations. in this case, the slave selects for the slaves controlled by this spi peripheral should be generated with general i/o pins. spi master operating modes the double buffered receive and transmit registers can be used to maximize the throughput of the spi peripheral by continuously streaming out data in master mode. the continuous transmit mode is designed to use the full capacity of the spi. in this mode, the ma ster will transmit and receive data until the spi/i2c transmit buffer sfr (spi2ctx, 0x9a) register is empty at the start of a byte transfer. continuous mode is enabled by setting the spicont bit in the spi configuration register sfr (spimod2, 0xe9) .the spi peripheral also offers a single byte read and a single byte write function. in master mode, the type of transfer is handled automatically depending on the configuration of bits 0 and 7 of the spi configuration register sfr (spimod2, 0xe9) . table 127 shows the sequence of events that should be performed for each master operating mode. based on the ss configuration, some of these events will take place automatically. table 127. procedures for using spi as a master mode spimod[7] = spicont bit spimod[0] = timode description of operation step1: read spirx sfr step2: ss is asserted low and read routine is initiated step 3: spirxirq interrupt flag is set when the spirx sfr is full step 4: ss is deasserted high single byte read 0 0 step 5: read spirx sfr to clear spirxirq interrupt flag step 1: write to spitx sfr step 2: ss is asserted low and write routine is initiated step 3: spitxirq interrupt flag is set when spitx re gister is empty step 4: ss is deasserted high single byte write 0 1 step 5: write to spitx sfr to clear spitxirq interrupt flag
preliminary technical data ade7169f16 rev. prd | page 127 of 140 step 1: write to spitx sfr step 2: ss is asserted low and write routine is initiated step 3: wait for spitxirq interrupt flag to write to spitx sfr. transfer will continue until the spitx register and transmit shift registers are empty. step 4: spitxirq interrupt flag is set when sfrtx register is empty step 5: ss is deasserted high continuous 1 1 step 6: write to spitx sfr to clear spitxirq interrupt flag figure 82 shows the spi output for certain automatic chip select and continuous mode selections. note that if the continuous mode is not used, a short delay is inserted between transfers. sclk ss dout din din1 din2 auto_ss=1 spicont=0 sclk ss dout din din1 auto_ss=1 spicont=1 din2 auto_ss=0 spicont=0 (manual ss control) dout1 dout2 dout1 dout2 sclk ss dout din din1 din2 dout1 doutz2 figure 82: automatic chip select and continuous mode output spi interrupt and status flags the spi interface has several status flags that indicate the status of the double buffered receive and transmit registers. figure 83 shows when the status and interrupt flags are raised. the transmit interrupt occurs when the transmit shift register is loaded with the data in the spi/i2c transmit buffer sfr (spi2ctx, 0x9a) register. if the spi master is in transmit operating mode and the spi/i2c transmit buffer sfr (spi2ctx, 0x9a) register has not been written with new data by the beginning of the next byte transfer, the transmit operation stops. when a new byte of data is received in the spi receive buffer sfr (spi2crx, 0x9b) register, the spi receive interrupt flag is raised. if the data in the spi receive buffer sfr (spi2crx, 0x9b) register is not read before new data is ready to be loaded into the spi receive buffer sfr (spi2crx, 0x9b), an overflow condition has occurred. this overflow condition, indicated by the spirxof flag, will force the new data to be discarded or overwritten if the rxof_en bit is set. spitx transmit shift register spitxirq=1 spitx (empty) transmit shift register stops transfer if timode=1 spirx receive shift register spirxirq=1 spirx (full) receive shift register spirxof=1 figure 83: spi receive and transmit interrupt and status flags
ade7169f16 preliminary technical data rev. prd | page 128 of 140 sclk (spicpol = 0) miso msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? sclk (spicpol = 1) mosi msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? spirx1 and spitx1 flags ss_b spirx0 and spitx0 flags spicpha = 1 miso msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? mosi msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? spirx1 and spitx1 flags spirx0 and spitx0 flags spicpha = 0 figure 84. spi timing configurations
preliminary technical data ade7169f16 rev. prd | page 129 of 140 i 2 c compatible interface the ade7169f16 supports a fully licensed * i 2 c interface. the i 2 c interface is implemented as a full hardware master. sdata is the data i/o pin, and sclk is the serial clock. these two pins are shared with the mosi and sclk pins of the on- chip spi interface. therefore, the user can enable only one interface or the other on these pins at any given time. the scps bit in the cfg sfr selects which peripheral is active. the two pins used for data transfer, sda and scl are configured in a wired-and format that allows arbitration in a multi-master system. the transfer sequence of a i2c system consists of a master device initiating a transfer by generating a start condition while the bus is idle. the master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. if the slave acknowledges then the data transfer is initiated. this continues until the master issues a stop condition and the bus becomes idle. serial clock generation the i 2 c master in the system generates the serial clock for a transfer. the master channel can be configured to operate in fast mode (256 khz) or standard mode (32 khz). the bit-rate is defined in the i2cmode sfr as follow: ] 0 : 1 [ 2 16 scldiv core scl f f = slave addresses the i2cadr sfr contains the slave device id. the lsb of this register contains a read/write re quest. a write to this sfr will start the i 2 c communication. i2c sfr register list the i 2 c peripheral interface consists of five sfrs: - i2cmod - spi2cstat - i2cadr - spi2ctx - spi2crx. as the spi and i2c serial interfaces share the same pins, i2cmod e, spi2cstat, spi2ctx and spi2crx sfrs are also shared with spimode1, spi2cstat, spitx and spirx sfrs respectively. sfr address name r/w length default value description 0x9a spi2ctx w 8 spi data out register 0x9b spi2crx r 8 0 spi data in register 0xe8 i2cmod r/w 8 0 spi configuration register 0xe9 i2cadr r/w 8 0 spi configuration register 0xea spi2cstat r/w 8 0 spi/i2c interrupt status register table 128: spi sfr register list table 129. i2c mode register sfr (i2cmod, 0xe8) bit location bit addr. bit name default value description 7 0xef i2cen 0 i2c enable bit when this bit is set to logic one, the i2c interface is enabled. a write to the i2cadr sfr will start a communication 6-5 0xee C 0xed i2cr[1:0] 0 i2c sclk frequency [1:0]
ade7169f16 preliminary technical data rev. prd | page 130 of 140 00 f core / 16 = 256khz if f core = 4.096mhz 01 f core / 32 = 128khz if f core = 4.096mhz 10 f core / 64 = 624hz if f core = 4.096mhz 11 f core / 128= 32khz if f core = 4.096mhz 4-0 0xec C oxe8 i2crct[4:0] 0 configures the length of the i2c received fifo buffer. the i2c peripheral will stop when i2crct[4:0] + 1 bytes have been read or if an error has occured table 130. i2c slave address sfr (i2cadr, 0xe9) bit location bit mnemonic default value description 7-1 i2cslvadr 0 address of the i2c slave being adressed writing to this register start the i2c transmission (read or write) 0 i2cr_w 0 command bit for read or write when this bit is set to logic one, a read command will be transmitted on the i2c bus. data from slave in spi2crx sfr is expected after command byte when this bit is set to logic zero, a write command will be transmitted on the i2c bus. data to slave is expected in spi2ctx sfr table 131. i2c interrupt status register sfr (i2cstat, 0xea) bit location bit mnemonic default value description 7 i2cbusy 0 this bit is set to logic one when the i2 c interface is used. when set, the tx fifo is emptied 6 i2cnoack 0 i2c no acknlowle dgement transmit interrupt this bit is set to logic one when the slave device did not send an acknlowledgement. the i2c communication is stopped after this event. erased by clearing bit. 5 i2crxirq 0 i2c receive interrupt this bit is set to logic one when the receive fifo is not empty this bit is cleared to logic zero by reading the spi2crx sfr and the fifo is empty 4 i2ctxirq 0 i2c transmit interrupt this bit is set to logic one wh en the transmit fifo is empty this bit is cleared to logic zero by writing to the spi2ctx sfr 3-2 i2cfifostat[1:0] 0 status bit for 3 or 4 bytes deep i2c fifo. the fifo monitored in these 2 bits is the one currently used in i2 c communication (receive or transmit) as only one of them is active at a time [1:0] 00 fifo empty 01 reserved 10 fifo half full 11 fifo full 1 i2cacc_err 0 set when trying to write and read at the same time 0 i2ctxwr_err 0 set when write was attempted when i2c transmit fifo was full an i2c interrupt occurs * purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use the ade7xxx in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. read and write operations figure 85 and figure 86 depict i2c read and write operations, respectively. note that the lsb of the i2cadr register is used to select
preliminary technical data ade7169f16 rev. prd | page 131 of 140 whether a read or write operation is performed on the slave device. during the read operation, the master acknowledges are gene rated automatically by the i2c peripheral. the master generated nack before the end of a read operation is also generated automatical ly after i2crct[4:0] bytes have been read from the slave. if the i2cadr register is updated during a transmission, instead of generating a stop at the end of the read or write operation, the master will generate a start condition and continue with the next communication. stop by master scl sda start by master ack by slave ack by master frame 2 data byte 1 from slave frame 1 serial bus address byte a6 19 9 1 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 r/w d7 nack by master frame n+1 data byte n from slave 9 1 d6 d5 d4 d3 d2 d1 d0 d7 figure 85: i2c read operation scl sda start by master ack by slave ack by slave frame 2 data byte 1 from master frame 1 serial bus address byte a6 19 9 1 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 stop by master r/w d7 figure 86: i2c write operation i2c receive and transmit fifos the i2c peripheral has a four byte receive fifo and a four byte transmit fifo. the buffers reduce the overhead associated with using the i2c peripheral. figure 87 shows the operation of the i2c receive and transmit fifos. the tx fifo can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation. when the transmit fifo is empty, the i2c transmit interrupt flag will be set and the pc will vector to the i2c interrupt vector if this interrupt is enabled. if a new byte is not loaded into the tx fifo before it is needed in the transmit shift register, the communication will stop. an error such as not receiving an acknowledge will also cause the communication to terminate. in case of an error during a write operation, the tx fifo will be flushed. the rx fifo allows four bytes to be read in from the slave before the mcu has to read the data. a receive interrupt can be generated after each byte is received or when the rx fifo is full. if the peripheral is reading from a slave address, the communication will stop once the number of received bytes equals the number set in the i2crct[4:0] bits. an error such as not receiving an acknowledge will also cause the communication to terminate. i2ctx txdata3 txdata2 txdata1 transmit shift register 4 byte fifo mov i2ctx, txdata1 mov i2ctx, txdata2 mov i2ctx, txdata3 code to fill tx fifo: i2ctx txdata3 txdata2 txdata1 transmit shift register mov i2ctx, txdata1 mov i2ctx, txdata2 mov i2ctx, txdata3 mov i2ctx, txdata4 code to fill tx fifo: i2crx rxdata1 rxdata2 rxdata3 rxdata4 receive shift register 4 byte fifo mov a, i2crx ; result: a=rxdata1 mov a, i2crx ; result: a=rxdata2 mov a, i2crx ; result: a=rxdata3 mov a, i2crx ; result: a=rxdata4 code to read rx fifo: txdata4 figure 87: i2c fifo operation
ade7169f16 preliminary technical data rev. prd | page 132 of 140 dual data pointers the ade7169f16 incorporates two data pointers. the second data pointer is a shadow data pointer and is selected via the data pointer control sfr (dpcon). dpcon features automatic hardware post-increment and post-decrement as well as an automatic data pointer toggle. table 132. data pointer control sfr sfr (dpcon, 0xa7) bit location bit mnemonic default va lu e description 7 ---- 0 not implemented. write dont care. 6 dpt 0 data pointer automatic toggle enable. cleared by the user to disable auto swapping of the dptr. set in user software to enable automatic toggling of the dptr after each movx or movc instruction. dp1m1, dp1m0 0 shadow data pointer mode. these bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution. dp1m1 dp1m0 behavior of the shadow data pointer 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 5, 4 1 1 dptr lsb is toggled after a movx or movc instruction. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) dp0m1, dp0m0 0 main data pointer mode. these bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution. dp0m1 dp0m0 behavior of the main data pointer 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 3, 2 1 1 dptr lsb is toggled after a movx or movc instruction. (this instruction is useful for moving 8-bit blocks to/from 16-bit devices.) 1 ---- 0 not implemented. write dont care. 0 dpsel 0 data pointer select. cleared by the user to select the main data pointer. this means that the contents of this 16- bit register are placed into the dpl, and dph sfrs. set by the user to select the shadow data pointer. this means that the contents of a separate 16-bit register appear in the dpl, and dph sfrs. note the following: ? the dual data pointer section is the only place in which main and shadow data pointers are distinguished.
preliminary technical data ade7169f16 rev. prd | page 133 of 140 whenever the dptr is mentioned elsewhere in this data sheet, active dptr is implied. ? only the movc/movx @dptr instructions automatically post-increment and post-decrement the dptr. other movc/movx instructions, such as movc pc or movc @ri, do not cause the dptr to automatically post-increment and post-decrement. to illustrate the operation of dpcon, the following code copies 256 bytes of code memory at address d000h into xram, starting from address 0000h. mov dptr,#0 ;main dptr = 0 mov dpcon,#55h ;select shadow dptr ;dptr1 increment mode ;dptr0 increment mode ;dptr auto toggling on mov dptr,#0d000h ;dptr = d000h moveloop: clr a movc a,@a+dptr ;get data ;post inc dptr ;swap to main dptr(data) movx @dptr,a ;put acc in xram ;increment main dptr ;swap shadow dptr(code) mov a, dpl jnz moveloop
ade7169f16 preliminary technical data rev. prd | page 134 of 140 i/o ports parallel i/o the ade7169f16 uses three input/output ports to exchange data with external devices. in addition to performing general- purpose i/o, some are capable of driving an lcd or performing other alternate functions for the peripheral functions available on-chip. in general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose i/o. the i/o port can be configured through the sfrs in table 133. table 133. i/o port sfrs sfr address bit addressable description p0 0x80 yes port 0 register p1 0x90 yes port 1 register p2 0xa0 yes port 2 register epcfg 0x9f no extended port configuration pinmap0 0xb2 no port 0 weak pull-up enable pinmap1 0xb3 no port 1 weak pull-up enable pinmap2 0xb4 no port 2 weak pull-up enable the three bidirectional i/o ports have internal pull-ups that can be enabled or disabled individually for each pin. the internal pull-ups are enabled by default. disabling an internal pull-up causes a pin to become open-drain. weak internal pull-ups are configured through pinmapx sfrs. read latch internal bus write to latch read pin d cl q latch dv dd px.x pin internal pull-up alternate output function alternate input function q closed: pinmapx.x= 0 open: pinmapx.x=1 figure 88. port 0 bit latch and i/o buffer figure 88 shows a typical bit latch and i/o buffer for an i/o pin. the bit latch (one bit in the ports sfr) is represented as a type d flip-flop, which clocks in a value from the internal bus in response to a write to latch signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a read latch signal from the cpu. the level of the port pin itself is placed on the internal bus in response to a read pin signal from the cpu. some instructions that read a port activate the read latch signal, and others activate the read pin signal. see the read-modify-write instructions section for details. weak internal pullups enabled a pin with the weak internal pull-up enabled is used as an input by writing a 1 is written to the pin. the pin will be pulled high by the internal pull-ups and the pin will be read using the circuitry shown in figure 88. if the pin is driven low externally, it will source current because of the internal pull-ups. if used as an output, a pin with an internal pull-up enabled, will be written with a 1 or a 0 to control the level of the output. if a 0 is written to the pin, it will drive a logic low output voltage (v ol ) and is capable of sinking tbd ma. open drain (weak internal pull-ups disabled) when the weak internal pull-up on a pin is disabled, the pin becomes open drain. to use this open-drain pin as a high impedance input, a 1 is written to the pin. the pin will be read using the circuitry shown in figure 88. the open drain option is preferable for inputs because it draws less current than the internal pull-ups were enabled. to use an open-drain pin as a general purpose output, an external pull-up resistor is required. open drain outputs are convenient for changing the voltage to a logic high. the ade7169f16 is a 3.3v device so an external resistor pulled up to 5v may ease interfacing to a 5v ic although most 5v ics are tolerant of 3.3v inputs. pins with 0s written to them drive a logic low output voltage (v ol ) and are capable of sinking 1.6 ma. 38 khz modulation the ade7169f16 provides a 38 khz modulation signal. the 38 khz modulation is accomplished by internally xoring the level written to the mod38 pin with a 38 khz square wave. then when a zero is written to the mod38 pin, it is modulated as shown in figure 89. 3 8khz modulation signal output at mod38 pin level written to mod38 figure 89: 38 khz modulation uses for this 38 khz modulation include ir modulation of a uart transmit signal or a low power signal to drive a led. the modulation can be enabled or disabled with the mod38en bit in the cfg sfr. the 38 khz modulation is available on eight pins, selected by the mod38[7:0] bits in the extended port configuration sfr (epcfg, 0x9f).
preliminary technical data ade7169f16 rev. prd | page 135 of 140 i/o sfr register list table 134. extended port configuration sfr (epcfg, 0x9f) bit location bit mnemonic default value description 7 mod38_fp21 0 enable 38khz modulation on p1.6/fp21 pin 6 mod38_fp22 0 enable 38khz modulation on p1.5/fp22 pin 5 mod38_fp23 0 enable 38khz modulation on p1.4/fp23/t2 pin 4 mod38_txd 0 enable 38khz modulation on p1.1/tx pin 3 mod38_cf1 0 enable 38khz modulation on p0.2/cf1 pin 2 mod38_ssb 0 enable 38khz modulation on p0.7/ss /t1pin 1 mod38_miso 0 enable 38khz modulation on p0.5/miso pin 0 mod38_cf2 0 enable 38khz modulation on p0.3/cf2 pin table 135. port 0 weak pull-up enable sfr (pinmap0, 0xb2) bit location bit mnemonic default value description 7 pinmap0.7 0 the weak pull-up on p0.7 is disabled when this bit is set 6 pinmap0.6 0 the weak pull-up on p0.6 is disabled when this bit is set 5 pinmap0.5 0 the weak pull-up on p0.5 is disabled when this bit is set 4 pinmap0.4 0 the weak pull-up on p0.4 is disabled when this bit is set 3 pinmap0.3 0 the weak pull-up on p0.3 is disabled when this bit is set 2 pinmap0.2 0 the weak pull-up on p0.2 is disabled when this bit is set 1 pinmap0.1 0 the weak pull-up on p0.1 is disabled when this bit is set 0 pinmap0.0 0 the weak pull-up on p0.0 is disabled when this bit is set table 136. port 1 weak pull-up enable sfr (pinmap1, 0xb3) bit location bit mnemonic default value description 7 pinmap1.7 0 the weak pull-up on p1.7 is disabled when this bit is set 6 pinmap1.6 0 the weak pull-up on p1.6 is disabled when this bit is set 5 pinmap1.5 0 the weak pull-up on p1.5 is disabled when this bit is set 4 pinmap1.4 0 the weak pull-up on p1.4 is disabled when this bit is set 3 pinmap1.3 0 the weak pull-up on p1.3 is disabled when this bit is set 2 pinmap1.2 0 the weak pull-up on p1.2 is disabled when this bit is set 1 pinmap1.1 0 the weak pull-up on p1.1 is disabled when this bit is set 0 pinmap1.0 0 the weak pull-up on p1.0 is disabled when this bit is set table 137. port 2 weak pull-up enable sfr (pinmap2, 0xb4) bit location bit mnemonic default value description 7 - 6 reserved 0 reserved. should be left cleared 5 pinmap2.5 0 the weak pull-up on rese t is disabled when this bit is set 4 reserved 0 the weak pull-up on ea is disabled when this bit is set 3 pinmap2.3 0 reserved. should be left cleared 2 pinmap2.2 0 the weak pull-up on p2.2 is disabled when this bit is set 1 pinmap2.1 0 the weak pull-up on p2.1 is disabled when this bit is set 0 pinmap2.0 0 the weak pull-up on p2.0 is disabled when this bit is set table 138. port 0 sfr (p0, 0x80) note: when an alternate function is chos en for a pin of this port, the bit controlling this pin should always be set
ade7169f16 preliminary technical data rev. prd | page 136 of 140 bit location bit addr. bit name default value description 7 0x87 t1 1 this bit reflects the state of p0.7/ss /t1 pin. it can be written or read. 6 0x86 t0 1 this bit reflects the state of p0 .6/sclk/t0 pin. it can be written or read. 5 0x85 1 this bit reflects the state of p0.5/miso pin. it can be written or read. 4 0x84 1 this bit reflects the state of p0.4 /mosi/sdata pin. it can be written or read. 3 0x83 cf2 1 this bit reflects the state of p0.3/cf2 pin. it can be written or read. 2 0x82 cf1 1 this bit reflects the state of p0.2/cf1 pin. it can be written or read. 1 0x81 1 this bit reflects the state of p0.1 pin. it can be written or read. 0 0x80 int1 1 this bit reflects the state of p0.0/int1 /bctrl pin. it can be written or read. table 139. port 1 sfr (p1, 0x90) note: when an alternate function is chos en for a pin of this port, the bit controlling this pin should always be set bit location bit addr. bit name default value description 7 0x97 1 this bit reflects the state of p1.7 pin. it can be written or read. 6 0x96 1 this bit reflects the state of p1.6 pin. it can be written or read. 5 0x95 1 this bit reflects the state of p1.5 pin. it can be written or read. 4 0x94 t2 1 this bit reflects the state of p1.4/t2 pin. it can be written or read. 3 0x93 t2ex 1 this bit reflects the state of p1.3/t2ex pin. it can be written or read. 2 0x92 1 this bit reflects the state of p1.2 pin. it can be written or read. 1 0x91 txd 1 this bit reflects the state of p1.1/txd pin. it can be written or read. 0 0x90 rxd 1 this bit reflects the state of p1.0/rxd pin. it can be written or read. table 140. port 2 sfr (p2, 0xa0) note: when an alternate function is chos en for a pin of this port, the bit controlling this pin should always be set bit location bit addr. bit name default value description 7 - 2 0x97 C 0x92 0x3f these bits are unused and should be left set 1 0x91 p2.1 1 this bit reflects the state of p2.1 pin. it can be written or read. 0 0x90 p2.0 1 this bit reflects the state of p2.0 pin. it can be written or read. table 141. port 0 alternate functions pin no. alternate function alternate function enable bctrl external battery control input set int1prog[2:0]=x01 in the interrupt pins configuration sfr (intpr, 0xff) int1 external interrupt set ex1 in the interrupt enable sfr (ie, 0xa8). p0.0 int1 wakeup from psm2 operating mode set int1prog [2:0]=11x in the interrupt pins configuration sfr (intpr, 0xff) p0.1 fp19 lcd segment pin set fp19en in the lcd segment enable 2 sfr (lcdsege2, 0xed) p0.2 cf1 ade calibration frequency output clear the discf1 bit in the ade energy measurement internal mode1 register (0x0b) p0.3 cf2 ade calibration frequency output clear the discf2 bit in the ade energy measurement internal mode1 register (0x0b) mosi spi data line set the scps bit in the cfg sfr and set the spien bit in the spi configuration register sfr (spimod1, 0xe8). p0.4 sdata i 2 c data line clear the scps bit in the configuration sfr (cfg, 0xaf) and set the i2cen bit in the i2c mode register sfr (i2cmod, 0xe8).
preliminary technical data ade7169f16 rev. prd | page 137 of 140 p0.5 miso spi data line set the scps bit in the configuration sfr (cfg, 0xaf) and set the spien bit in the spi configuration register sfr (spimod2, 0xe9) sclk serial clock for i 2 c or spi set the i2cen bit in the i2cmod sfr or the spien bit in the spi configuration register sfr (spimod2, 0xe9) to enable the i 2 c or spi interface p0.6 t0 timer0 input set the cnt0 bit in the timer/counter 0 and 1 mode sfr (tmod, 0x89) to enable t0 as an external event counter ss spi slave select input for spi in slave mode set th e ss_en bit in the spi configuration register sfr (spimod1, 0xe8) ss spi slave select output for spi in master mode set the spims_b bit in the spi configuration register sfr (spimod2, 0xe9) p0.7 t1 timer 1 input set the cnt1 bit in the timer/counter 0 and 1 mode sfr (tmod, 0x89) to enable t1 as an external event counter table 142. port 1 alternate functions pin no. alternate function alternate function enable rxd receiver data input for uart set the ren bit in the scon sfr bit description sfr (scon, 0x98). p1.0 rx edge wakeup from psm2 operating mode set rxprog[1:0]=11 in the peripheral configuration sfr (periph, 0xf4) p1.1 txd transmitter da ta output for uart p1.2 fp25 lcd segment pin set fp25en in th e lcd segment enable sfr (lcdsege, 0x97) fp24 lcd segment pin set fp24en in the lc d segment enable sfr (lcdsege, 0x97) p1.3 t2ex timer 2 control input set exen2 in th e timer/counter 2 control sfr (t2con, 0xc8) fp23 lcd segment pin set fp23en in the lc d segment enable sfr (lcdsege, 0x97) p1.4 t2 timer 2 input set the cnt2 bit in the timer/counter 2 control sfr (t2con, 0xc8) to enable t2 as an external event counter p1.5 fp22 lcd segment pin set fp22en in th e lcd segment enable sfr (lcdsege, 0x97) p1.6 fp21 lcd segment pin set fp21en in th e lcd segment enable sfr (lcdsege, 0x97) p1.7 fp20 lcd segment pin set fp20en in th e lcd segment enable sfr (lcdsege, 0x97) table 143. port 2 alternate functions pin no. alternate function alternate function enable p2.0 fp18 lcd segment pin set fp18en in the lcd segment enable 2 sfr (lcdsege2, 0xed) p2.1 fp17 lcd segment pin set fp17en in the lcd segment enable 2 sfr (lcdsege2, 0xed) p2.2 fp16 lcd segment pin set fp16en in the lcd segment enable 2 sfr (lcdsege2, 0xed) p2.3 sden serial download pin sampled on reset. p2.3 is an output only. enabled by default. port 0 port 0 is controlled directly through the bit-addressable port 0 sfr (80h). the weak internal pull-ups for port 0 are configure d through the port 0 weak pull-up enable sfr (pinmap0, 0xb2); they are enabled by default. disable the weak internal pull-up by writing a one to p0cfg..x. port 0 pins also have various secondary functions as described in table 141. the alternate functions of port 0 pins can be acti vated only if
ade7169f16 preliminary technical data rev. prd | page 138 of 140 the corresponding bit latch in the p0 sfr contains a 1. otherwise, the port pin remains at 0. port 1 port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable port 1 sfr (90h). the weak internal pull- ups for port 1 are configured through the port 1 weak pull-up enable sfr (pinmap1, 0xb3); they are enabled by default. disable the weak inte rnal pull-up by writing a one to p1cfg..x. port 1 pins also have various secondary functions as described in table 142. the alternate functions of port 1 pins can be acti vated only if the corresponding bit latch in the p1 sfr contains a 1. otherwise, the port pin remains at 0. port 2 port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable port 2 sfr (a0h). note that p2.3 can be us ed as an output only. the weak internal pull-ups for port 2 are configured through the port 2 weak pull-up enable sfr (pinmap2, 0xb4); t hey are enabled by default. disable the weak internal pull-up by writing a one to p2cfg..x. port 2 pins also have various secondary functions as described in table 143. the alternate functions of port 2 pins can be acti vated only if the corresponding bit latch in the p2 sfr contains a 1. otherwise, the port pin remains at 0.
preliminary technical data ade7169f16 rev. prd | page 139 of 140 outline dimensions dimensions shown in millimeters
ade7169f16 preliminary technical data rev. prd | page 140 of 140 ordering guide table 144. model package description package option* temperature range ade7169astf16 64-lead lqfp lqfp-64 ?40c to +85c ade7169astzf16 64-lead lead free lqfp lqfp-64 ?40c to +85c ade7169astf16-rl 64-lead lqfp in reel lqfp-64 ?40c to +85c ADE7169ASTZF16-RL 64-lead lead free lqfp in reel lqfp-64 ?40c to +85c ade7169acpf16 64-lead csp lfcsp-64 ?40c to +85c ade7169acpzf16 64-lead lead free csp lfcsp-64 ?40c to +85c ade7169acpf16-rl 64-lead csp in reel lfcsp-64 ?40c to +85c ade7169acpzf16-rl 64-lead lead free csp in reel lfcsp-64 ?40c to +85c eval-ade7169f16eb ade7169 evaluation board ?40c to +85c ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06353-0-9/06(prd)

▲Up To Search▲

Price & Availability of ADE7169ASTZF16-RL

	To Download ADE7169ASTZF16-RL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .